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| 1. general description the P89V51RB2/rc2/rd2 are 80c51 microcontrollers with 16/32/64 kb ?ash and 1024 b of data ram. a key feature of the P89V51RB2/rc2/rd2 is its x2 mode option. the design engineer can choose to run the application with the conventional 80c51 clock rate (12 clocks per machine cycle) or select the x2 mode (six clocks per machine cycle) to achieve twice the throughput at the same clock frequency. another way to bene?t from this feature is to keep the same performance by reducing the clock frequency by half, thus dramatically reducing the emi. the ?ash program memory supports both parallel programming and in serial isp. parallel programming mode offers gang-programming at high speed, reducing programming costs and time to market. isp allows a device to be reprogrammed in the end product under software control. the capability to ?eld/update the application ?rmware makes a wide range of applications possible. the P89V51RB2/rc2/rd2 is also capable of iap, allowing the ?ash program memory to be recon?gured even while the application is running. 2. features n 80c51 cpu n 5 v operating voltage from 0 mhz to 40 mhz n 16/32/64 kb of on-chip ?ash user code memory with isp and iap n supports 12-clock (default) or 6-clock mode selection via software or isp n spi and enhanced uart n pca with pwm and capture/compare functions n four 8-bit i/o ports with three high-current port 1 pins (16 ma each) n three 16-bit timers/counters n programmable watchdog timer n eight interrupt sources with four priority levels n second dptr register n low emi mode (ale inhibit) n ttl- and cmos-compatible logic levels P89V51RB2/rc2/rd2 8-bit 80c51 5 v low power 16/32/64 kb ?ash microcontroller with 1 kb ram rev. 04 1 may 2007 product data sheet
P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 2 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core n brownout detection n low power modes u power-down mode with external interrupt wake-up u idle mode n dip40, plcc44 and tqfp44 packages 3. ordering information 3.1 ordering options table 1. ordering information type number package name description version P89V51RB2fa plcc44 plastic leaded chip carrier; 44 leads sot187-2 P89V51RB2fn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 P89V51RB2bbc tqfp44 plastic thin quad ?at package; 44 leads; body 10 10 1.0 mm sot376-1 p89v51rc2fa plcc44 plastic leaded chip carrier; 44 leads sot187-2 p89v51rc2fbc tqfp44 plastic thin quad ?at package; 44 leads; body 10 10 1.0 mm sot376-1 p89v51rc2fn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 p89v51rd2fa plcc44 plastic leaded chip carrier; 44 leads sot187-2 p89v51rd2fbc tqfp44 plastic thin quad ?at package; 44 leads; body 10 10 1.0 mm sot376-1 p89v51rd2bn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 p89v51rd2fn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 table 2. ordering options type number flash memory temperature range frequency P89V51RB2fa 16 kb - 40 cto+85 c 0 mhz to 40 mhz P89V51RB2fn 16 kb - 40 cto+85 c P89V51RB2bbc 16 kb 0 cto+70 c p89v51rc2fa 32 kb - 40 cto+85 c p89v51rc2fbc 32 kb - 40 cto+85 c p89v51rc2fn 32 kb - 40 cto+85 c p89v51rd2fa 64 kb - 40 cto+85 c p89v51rd2fbc 64 kb - 40 cto+85 c p89v51rd2bn 64 kb 0 cto+70 c p89v51rd2fn 64 kb - 40 cto+85 c P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 3 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 4. block diagram fig 1. block diagram high performance 80c51 cpu 16/32/64 kb code flash 1 kb data ram oscillator internal bus crystal or resonator 002aac772 uart port 2 spi timer 2 timer 0 timer 1 pca programmable counter array watchdog timer xtal1 xtal2 port 3 p3[7:0] p2[7:0] port 1 p1[7:0] port 0 p0[7:0] cex[4:0] txd rxd t0 t1 t2 t2ex spiclk mosi miso ss P89V51RB2/rc2/rd2 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 4 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 5. pinning information 5.1 pinning fig 2. plcc44 pin con?guration P89V51RB2fa p89v51rc2fa p89v51rd2fa p1.5/mosi/cex2 p0.4/ad4 p1.6/miso/cex3 p0.5/ad5 p1.7/sck/cex4 p0.6/ad6 rst p0.7/ad7 p3.0/rxd n.c. p3.1/txd p2.7/a15 p3.4/t0 p2.6/a14 p3.5/t1 p2.5/a13 p1.4/ss/cex1 p1.3/cex0 xtal2 p1.2/eci xtal1 p1.1/t2ex v ss p1.0/t2 n.c. n.c. p2.0/a8 v dd p2.1/a9 p0.0/ad0 p2.2/a10 p0.1/ad1 p2.3/a11 p0.2/ad2 p2.4/a12 p0.3/ad3 002aaa810 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 ea ale/prog psen p3.6/wr p3.7/rd p3.3/int1 p3.2/int0 n.c. P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 5 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fig 3. dip40 pin con?guration fig 4. tqfp44 pin con?guration P89V51RB2fn p89v51rc2fn p89v51rd2bn p89v51rd2fn p1.0/t2 v dd p1.1/t2ex p0.0/ad0 p1.2/eci p0.1/ad1 p1.3/cex0 p0.2/ad2 p1.4/ss/cex1 p0.3/ad3 p1.5/mosi/cex2 p0.4/ad4 p1.6/miso/cex3 p0.5/ad5 p1.7/sck/cex4 p0.6/ad6 rst p0.7/ad7 p3.0/rxd ea p3.1/txd ale/prog p3.2/int0 psen p3.3/int1 p2.7/a15 p3.4/t0 p2.6/a14 p3.5/t1 p2.5/a13 p3.6/wr p2.4/a12 p3.7/rd p2.3/a11 xtal2 p2.2/a10 xtal1 p2.1/a9 v ss p2.0/a8 002aaa811 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 21 24 23 26 25 40 39 38 37 36 35 34 33 32 31 30 29 28 27 P89V51RB2bbc p89v51rc2fbc p89v51rd2fbc p1.5/mosi/cex2 p0.4/ad4 p1.6/miso/cex3 p0.5/ad5 p1.7/sck/cex4 p0.6/ad6 rst p0.7/ad7 p3.0/rxd n.c. p3.1/txd p2.7/a15 p3.4/t0 p2.6/a14 p3.5/t1 p2.5/a13 p1.4/ss/cex1 p1.3/cex0 xtal2 p1.2/eci xtal1 p1.1/t2ex v ss p1.0/t2 n.c. n.c. p2.0/a8 v dd p2.1/a9 p0.0/ad0 p2.2/a10 p0.1/ad1 p2.3/a11 p0.2/ad2 p2.4/a12 p0.3/ad3 002aaa812 ea ale/prog psen p3.6/wr p3.7/rd p3.3/int1 p3.2/int0 n.c. 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 6 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 5.2 pin description table 3. P89V51RB2/rc2/rd2 pin description symbol pin type description dip40 tqfp44 plcc44 p0.0 to p0.7 i/o port 0: port 0 is an 8-bit open drain bidirectional i/o port. port 0 pins that have 1s written to them ?oat, and in this state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. in this application, it uses strong internal pull-ups when transitioning to 1s. port 0 also receives the code bytes during the external host mode programming, and outputs the code bytes during the external host mode veri?cation. external pull-ups are required during program veri?cation or as a general purpose i/o port. p0.0/ad0 39 37 43 i/o p0.0 port 0 bit 0. i/o ad0 address/data bit 0. p0.1/ad1 38 36 42 i/o p0.1 port 0 bit 1. i/o ad1 address/data bit 1. p0.2/ad2 37 35 41 i/o p0.2 port 0 bit 2. i/o ad2 address/data bit 2. p0.3/ad3 36 34 40 i/o p0.3 port 0 bit 3. i/o ad3 address/data bit 3. p0.4/ad4 35 33 39 i/o p0.4 port 0 bit 4. i/o ad4 address/data bit 4. p0.5/ad5 34 32 38 i/o p0.5 port 0 bit 5. i/o ad5 address/data bit 5. p0.6/ad6 33 31 37 i/o p0.6 port 0 bit 6. i/o ad6 address/data bit 6. p0.7/ad7 32 30 36 i/o p0.7 port 0 bit 7. i/o ad7 address/data bit 7. p1.0 to p1.7 i/o with internal pull-up port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. the port 1 pins are pulled high by the internal pull-ups when 1s are written to them and can be used as inputs in this state. as inputs, port 1 pins that are externally pulled low will source current (i il ) because of the internal pull-ups. p1.5, p1.6, p1.7 have high current drive of 16 ma. port 1 also receives the low-order address bytes during the external host mode programming and veri?cation. p1.0/t2 1 40 2 i/o p1.0 port 1 bit 0. i/o t2 external count input to timer/counter 2 or clock-out from timer/counter 2. p1.1/t2ex 2 41 3 i/o p1.1 port 1 bit 1. i t2ex : timer/counter 2 capture/reload trigger and direction control. P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 7 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core p1.2/eci 3 42 4 i/o p1.2 port 1 bit 2. i eci external clock input. this signal is the external clock input for the pca. p1.3/cex0 4 43 5 i/o p1.3 port 1 bit 3. i/o cex0 capture/compare external i/o for pca module 0. each capture/compare module connects to a port 1 pin for external i/o. when not used by the pca, this pin can handle standard i/o. p1.4/ ss/cex1 5 44 6 i/o p1.4 port 1 bit 4. i ss slave port select input for spi. i/o cex1 capture/compare external i/o for pca module 1. p1.5/mosi/ cex2 6 1 7 i/o p1.5 port 1 bit 5. i/o mosi master output slave input for spi. i/o cex2 capture/compare external i/o for pca module 2. p1.6/miso/ cex3 7 2 8 i/o p1.6 port 1 bit 6. i/o miso master input slave output for spi. i/o cex3 capture/compare external i/o for pca module 3. p1.7/sck/ cex4 8 3 9 i/o p1.7 port 1 bit 7. i/o sck master output slave input for spi. i/o cex4 capture/compare external i/o for pca module 4. p2.0 to p2.7 i/o with internal pull-up port 2 : port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins are pulled high by the internal pull-ups when 1s are written to them and can be used as inputs in this state. as inputs, port 2 pins that are externally pulled low will source current (i il ) because of the internal pull-ups. port 2 sends the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit address (movx@dptr). in this application, it uses strong internal pull-ups when transitioning to 1s. port 2 also receives some control signals and a partial of high-order address bits during the external host mode programming and veri?cation. p2.0/a8 21 18 24 i/o p2.0 port 2 bit 0. o a8 address bit 8. p2.1/a9 22 19 25 i/o p2.1 port 2 bit 1. o a9 address bit 9. p2.2/a10 23 20 26 i/o p2.2 port 2 bit 2. o a10 address bit 10. p2.3/a11 24 21 27 i/o p2.3 port 2 bit 3. o a11 address bit 11. p2.4/a12 25 22 28 i/o p2.4 port 2 bit 4. o a12 address bit 12. table 3. P89V51RB2/rc2/rd2 pin description continued symbol pin type description dip40 tqfp44 plcc44 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 8 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core p2.5/a13 26 23 29 i/o p2.5 port 2 bit 5. o a13 address bit 13. p2.6/a14 27 24 30 i/o p2.6 port 2 bit 6. o a14 address bit 14. p2.7/a15 28 25 31 i/o p2.7 port 2 bit 7. o a15 address bit 15. p3.0 to p3.7 i/o with internal pull-up port 3 : port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins are pulled high by the internal pull-ups when 1s are written to them and can be used as inputs in this state. as inputs, port 3 pins that are externally pulled low will source current (i il ) because of the internal pull-ups. port 3 also receives some control signals and a partial of high-order address bits during the external host mode programming and veri?cation. p3.0/rxd 10 5 11 i p3.0 port 3 bit 0. i rxd serial input port. p3.1/txd 11 7 13 o p3.1 port 3 bit 1. o txd serial output port. p3.2/ int0 12 8 14 i p3.2 port 3 bit 2. i int0 external interrupt 0 input. p3.3/ int1 13 9 15 i p3.3 port 3 bit 3. i int1 external interrupt 1 input. p3.4/t0 14 10 16 i/o p3.4 port 3 bit 4. i t0 external count input to timer/counter 0. p3.5/t1 15 11 17 i/o p3.5 port 3 bit 5. i t1 external count input to timer/counter 1. p3.6/ wr 16 12 18 o p3.6 port 3 bit 6. o wr external data memory write strobe. p3.7/ rd 17 13 19 o p3.7 port 3 bit 7. o rd external data memory read strobe. psen 29 26 32 i/o program store enable : psen is the read strobe for external program memory. when the device is executing from internal program memory, psen is inactive (high). when the device is executing code from external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. a forced high-to-low input transition on the psen pin while the rst input is continually held high for more than 10 machine cycles will cause the device to enter external host mode programming. table 3. P89V51RB2/rc2/rd2 pin description continued symbol pin type description dip40 tqfp44 plcc44 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 9 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core [1] ale loading issue: when ale pin experiences higher loading (>30 pf) during the reset, the microcontroller may accidentally enter into modes other than normal working mode. the solution is to add a pull-up resistor of 3 k w to 50 k w to v dd , e.g., for ale pin. [2] for 6-clock mode, ale is emitted at 1 3 of crystal frequency. rst 9 4 10 i reset : while the oscillator is running, a high logic state on this pin for two machine cycles will reset the device. if the psen pin is driven by a high-to-low input transition while the rst input pin is held high, the device will enter the external host mode, otherwise the device will enter the normal operation mode. ea 31 29 35 i external access enable : ea must be connected to v ss in order to enable the device to fetch code from the external program memory. ea must be strapped to v dd for internal program execution. however, security lock level 4 will disable ea, and program execution is only possible from internal program memory. the ea pin can tolerate a high voltage of 12 v. ale/ pr og 30 27 33 i/o address latch enable: ale is the output signal for latching the low byte of the address during an access to external memory. this pin is also the programming pulse input ( pr og) for ?ash programming. normally the ale [1] is emitted at a constant rate of 1 6 the crystal frequency [2] and can be used for external timing and clocking. one ale pulse is skipped during each access to external data memory. however, if ao is set to 1, ale is disabled. n.c. - 6, 17, 28, 39 1, 12, 23, 34 i/o not connected xtal1 19 15 21 i crystal 1 : input to the inverting oscillator ampli?er and input to the internal clock generator circuits. xtal2 18 14 20 o crystal 2: output from the inverting oscillator ampli?er. v dd 40 38 44 i power supply v ss 20 16 22 i ground table 3. P89V51RB2/rc2/rd2 pin description continued symbol pin type description dip40 tqfp44 plcc44 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 10 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6. functional description 6.1 special function registers remark: sfr accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not de?ned. ? accesses to any de?ned sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled -, 0 or 1 can only be written and read as follows: C - unless otherwise speci?ed, must be written with 0, but can return any value when read (even if it was written with 0). it is a reserved bit and may be used in future derivatives. C 0 must be written with 0, and will return a 0 when read. C 1 must be written with 1, and will return a 1 when read. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 11 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core table 4. special function registers * indicates sfrs that are bit addressable name description sfr address bit functions and addresses msb lsb bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h auxr auxiliary function register 8eh ------ extram ao auxr1 auxiliary function register 1 a2h - - - gf2 0 - dps bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h ccap0h module 0 capture high fah ccap1h module 1 capture high fbh ccap2h module 2 capture high fch ccap3h module 3 capture high fdh ccap4h module 4 capture high feh ccap0l module 0 capture low eah ccap1l module 1 capture low ebh ccap2l module 2 capture low ech ccap3l module 3 capture low edh ccap4l module 4 capture low eeh ccapm0 module 0 mode dah - ecom_0 capp_0 capn_0 mat_0 tog_0 pwm_0 eccf_0 ccapm1 module 1 mode dbh - ecom_1 capp_1 capn_1 mat_1 tog_1 pwm_1 eccf_1 ccapm2 module 2 mode dch - ecom_2 capp_2 capn_2 mat_2 tog_2 pwm_2 eccf_2 ccapm3 module 3 mode ddh - ecom_3 capp_3 capn_3 mat_3 tog_3 pwm_3 eccf_3 ccapm4 module 4 mode deh - ecom_4 capp_4 capn_4 mat_4 tog_4 pwm_4 eccf_4 bit address df de dd dc db da d9 d8 ccon* pca counter control d8h cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 ch pca counter high f9h cl pca counter low e9h cmod pca counter mode d9h cidl wdte - - - cps1 cps0 ecf dptr data pointer (2 b) dph data pointer high 83h dpl data pointer low 82h xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 12 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fst flash status register b6 - sb - - edc - - - bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ec et2 es0 et1 ex1 et0 ex0 bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h ----ebo bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority b8h - ppc pt2 ps pt1 px1 pt0 px0 ip0h interrupt priority 0 high b7h - ppch pt2h psh pt1h px1h pt0h px0h bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h ----pbo ip1h interrupt priority 1 high f7h ---- pboh fcf b1h------swr bsel bit address 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 bit address 97 96 95 94 93 92 91 90 p1* port 1 90h cex4/ spiclk cex3/ miso cex2/ mosi cex1/ ss cex0 eci t2ex t2 bit address a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h a15 a14 a13 a12 a11 a10 a9 a8 bit address b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h rd wr t1 t0 int1 int0 txd rxd pcon power control register 87h smod1 smod0 bof pof gf1 gf0 pd idl bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p rcap2h timer2 capture high cbh rcap2l timer2 capture low cah bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0/fe_ sm1 sm2 ren tb8 rb8 ti ri sbuf serial port data buffer register 99h table 4. special function registers continued * indicates sfrs that are bit addressable name description sfr address bit functions and addresses msb lsb xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 13 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core [1] unimplemented bits in sfrs (labeled -) are xs (unknown) at all times. unless otherwise speci?ed, 1s should not be writt en to these bits since they may be used for other purposes in future derivatives. the reset values shown for these bits are 0s although they are unknown when read. saddr serial port address register a9h saden serial port address enable b9h bit address 87 [1] 86 [1] 85 [1] 84 [1] 83 [1] 82 [1] 81 [1] 80 [1] spctl spi control register d5h spie spen dord mstr cpol cpha spr1 spr0 spcfg spi con?guration register aah spif spwcol - - ---- spdat spi data 86h sp stack pointer 81h bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control register 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit address cf ce cd cc cb ca c9 c8 t2con* timer2 control register c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 t2mod timer2 mode control c9h - - ent2 t2oe dcen th0 timer 0 high 8ch th1 timer 1 high 8dh th2 timer 2 high cdh tl0 timer 0 low 8ah tl1 timer 1 low 8bh tl2 timer 2 low cch tmod timer 0 and 1 mode 89h gate c/t m1 m0 gate c/t m1 m0 wdtc watchdog timer control c0h - - - wdout wdre wdts wdt swdt wdtd watchdog timer data/reload 85h table 4. special function registers continued * indicates sfrs that are bit addressable name description sfr address bit functions and addresses msb lsb P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 14 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.2 memory organization the device has separate address spaces for program and data memory. 6.2.1 flash program memory bank selection there are two internal ?ash memory blocks in the device. block 0 has 16/32/64 kb and is organized as 128/256/512 sectors, each sector consists of 128 b. block 1 contains the iap/isp routines and may be enabled such that it overlays the ?rst 8 kb of the user code memory. the overlay function is controlled by the combination of the software reset bit (swr) at fcf.1 and the bank select bit (bsel) at fcf.0. the combination of these bits and the memory source used for instructions is shown in t ab le 5 . access to the iap routines in block 1 may be enabled by clearing the bsel bit (fcf.0), provided that the swr bit (fcf.1) is cleared. following a power-on sequence, the boot code is automatically executed and attempts to auto baud to a host. if no auto baud occurs within approximately 400 ms and the softice ?ag is not set, control will be passed to the user code. a software reset is used to accomplish this control transfer and as a result the swr bit will remain set. therefore the user's code will need to clear the swr bit in order to access the iap routines in block 1. however, caution must be taken when dynamically changing the bsel bit. since this will cause different physical memory to be mapped to the logical program address space, the user must avoid clearing the bsel bit when executing user code within the address range 0000h to 1fffh. 6.2.2 power-on reset code execution at initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins high. powering up the device without a valid reset could cause the mcu to start executing instructions from an indeterminate location. such unde?ned states may inadvertently corrupt the code in the ?ash. a system reset will not affect the 1 kb of on-chip ram while the device is running, however, the contents of the on-chip ram during power up are indeterminate. when power is applied to the device, the rst pin must be held high long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. an example of a method to extend the rst signal is to implement a rc circuit by connecting the rst pin to v dd through a 10 m f capacitor and to v ss through an 8.2 k w resistor as shown in figure 5 . note that if an rc circuit is being used, provisions should be made to ensure the v dd rise time does not exceed 1 ms and the oscillator start-up time does not exceed 10 ms. for a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. this method maintains the necessary relationship between v dd and rst to avoid programming at an indeterminate location, which may cause corruption in the code of the ?ash. the power-on detection is designed table 5. code memory bank selection swr (fcf.1) bsel (fcf.0) addresses from 0000h to 1fffh addresses above 1fffh 0 0 bootcode (in block 1) user code (in block 0) 0 1 user code (in block 0) 10 11 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 15 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core to work during initial power up, before the voltage reaches the brownout detection level. the pof ?ag in the pcon register is set to indicate an initial power up condition. the pof ?ag will remain active until cleared by software. following a power-on or external reset the P89V51RB2/rc2/rd2 will force the swr and bsel bits (fcf[1:0]) = 00. this causes the boot block to be mapped into the lower 8 kb of code memory and the device will execute the isp code in the boot block and attempt to auto baud to the host. if the auto baud is successful the device will remain in isp mode. if, after approximately 400 ms, the auto baud is unsuccessful the boot block code will check to see if the softice ?ag is set (from a previous programming operation). if the softice ?ag is set the device will enter softice mode. if the softice ?ag is cleared, the boot code will execute a software reset causing the device to execute the user code from block 0 starting at address 0000h. note that an external reset applied to the rst pin has the same effect as a power-on reset. 6.2.3 software reset a software reset is executed by changing the swr bit (fcf.1) from 0 to 1. a software reset will reset the program counter to address 0000h and force both the swr and bsel bits (fcf[1:0]) = 10. this will result in the lower 8 kb of the user code memory being mapped into the user code memory space. thus the user's code will be executed starting at address 0000h. a software reset will not change wdtc.2 or ram data. other sfrs will be set to their reset values. 6.2.4 brownout detect reset the device includes a brownout detection circuit to protect the system from severe supply voltage ?uctuations. the P89V51RB2/rc2/rd2's brownout detection threshold is 2.35 v. when v dd drops below this voltage threshold, the brownout detect triggers the circuit to generate a brownout interrupt but the cpu still runs until the supplied voltage returns to the brownout detection voltage v bod . the default operation for a brownout detection is to cause a processor reset. fig 5. power-on reset circuit 002aaa543 v dd v dd 8.2 k w rst xtal2 xtal1 c 1 c 2 10 m f P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 16 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core v dd must stay below v bod at least four oscillator clock periods before the brownout detection circuit will respond. brownout interrupt can be enabled by setting the ebo bit (iea.3). if ebo bit is set and a brownout condition occurs, a brownout interrupt will be generated to execute the program at location 004bh. it is required that the ebo bit be cleared by software after the brownout interrupt is serviced. clearing ebo bit when the brownout condition is active will properly reset the device. if brownout interrupt is not enabled, a brownout condition will reset the program to resume execution at location 0000h. a brownout detect reset will clear the bsel bit (fcf.0) but will not change the swr bit (fcf.1) and therefore will not change the banking of the lower 8 kb of user code memory space. 6.2.5 watchdog reset like a brownout detect reset, the watchdog timer reset will clear the bsel bit (fcf.0) but will not change the swr bit (fcf.1) and therefore will not change the banking of the lower 8 kb of user code memory space. the state of the swr and bsel bits after different types of resets is shown in t ab le 6 . this results in the code memory bank selections as shown. 6.2.6 data ram memory the data ram has 1024 b of internal memory. the device can also address up to 64 kb for external data memory. 6.2.7 expanded data ram addressing the P89V51RB2/rc2/rd2 has 1 kb of ram. see figure 6 inter nal and e xter nal data memor y str ucture on page 19 . the device has four sections of internal data memory: 1. the lower 128 b of ram (00h to 7fh) are directly and indirectly addressable. 2. the higher 128 b of ram (80h to ffh) are indirectly addressable. 3. the special function registers (80h to ffh) are directly addressable only. 4. the expanded ram of 768 b (00h to 2ffh) is indirectly addressable by the move external instruction (movx) and clearing the extram bit (see auxiliary function register (auxr) in t ab le 4 special function registers on page 11 ). since the upper 128 b occupy the same addresses as the sfrs, the ram must be accessed indirectly. the ram and sfrs space are physically separate even though they have the same addresses. table 6. effects of reset sources on bank selection reset source swr bit result (fcf.1) bsel bit result (fcf.0) addresses from 0000h to 1fffh addresses above 1fffh external reset 0 0 boot code (in block 1) user code (in block 0) power-on reset watchdog reset x 0 retains state of swr bit. if swr, bsel = 00 then uses boot code. if swr, bsel = 10 then uses user code. brownout detect reset software reset 1 0 user code (in block 0) P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 17 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core when instructions access addresses in the upper 128 b (above 7fh), the mcu determines whether to access the sfrs or ram by the type of instruction given. if it is indirect, then ram is accessed. if it is direct, then an sfr is accessed. see the examples below. indirect access: mov@r0, #data; r0 contains 90h register r0 points to 90h which is located in the upper address range. data in #data is written to ram location 90h rather than port 1. direct access: mov90h, #data; write data to p1 data in #data is written to port 1. instructions that write directly to the address write to the sfrs. to access the expanded ram, the extram bit must be cleared and movx instructions must be used. the extra 768 b of memory is physically located on the chip and logically occupies the ?rst 768 b of external memory (addresses 000h to 2ffh). when extram = 0, the expanded ram is indirectly addressed using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. accessing the expanded ram does not affect ports p0, p3.6 ( wr), p3.7 ( rd), or p2. with extram = 0, the expanded ram can be accessed as in the following example. expanded ram access (indirect addressing only): movx@dptr, a dptr contains 0a0h table 7. auxr - auxiliary register (address 8eh) bit allocation not bit addressable; reset value 00h bit 7 6 5 4 3 2 1 0 symbol - - - - - - extram ao table 8. auxr - auxiliary register (address 8eh) bit description bit symbol description 7 to 2 - reserved for future use. should be set to 0 by user programs. 1 extram internal/external ram access using movx @ri/@dptr. when 0, core attempts to access internal xram with address speci?ed in movx instruction. if address supplied with this instruction exceeds on-chip available xram, off-chip xram is going to be selected and accessed. when 1, every movx @ri/@dptr instruction targets external data memory by default. 0 ao ale off: disables/enables ale. ao = 0 results in ale emitted at a constant rate of 1 2 the oscillator frequency. in case of ao = 1, ale is active only during a movx or movc. P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 18 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core dptr points to 0a0h and data in a is written to address 0a0h of the expanded ram rather than external memory. access to external memory higher than 2ffh using the movx instruction will access external memory (0300h to ffffh) and will perform in the same way as the standard 8051, with p0 and p2 as data/address bus, and p3.6 and p3.7 as write and read timing signals. when extram = 1, movx @ri and movx @dptr will be similar to the standard 8051. using movx @ri provides an 8-bit address with multiplexed data on port 0. other output port pins can be used to output higher order address bits. this provides external paging capabilities. using movx @dptr generates a 16-bit address. this allows external addressing up the 64 kb. port 2 provides the high-order eight address bits (dph), and port 0 multiplexes the low order eight address bits (dpl) with data. both movx @ri and movx @dptr generates the necessary read and write signals (p3.6 - wr and p3.7 - rd) for external memory use. t ab le 9 shows external data memory rd, wr operation with extram bit. the stack pointer (sp) can be located anywhere within the 256 b of internal ram (lower 128 b and upper 128 b). the stack pointer may not be located in any part of the expanded ram. [1] access limited to eram address within ospi to 0ffh; cannot access 100h to 02ffh. table 9. external data memory rd, wr with extram bit [1] auxr movx @dptr, a or movx a, @dptr movx @ri, a or movx a, @ri addr < 0300h addr 3 0300h addr = any extram = 0 rd/ wr not asserted rd/ wr asserted rd/ wr not asserted extram = 1 rd/ wr asserted rd/ wr asserted rd/ wr asserted P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 19 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.2.8 dual data pointers the device has two 16-bit data pointers. the dptr select (dps) bit in auxr1 determines which of the two data pointers is accessed. when dps = 0, dptr0 is selected; when dps = 1, dptr1 is selected. quickly switching between the two data pointers can be accomplished by a single inc instruction on auxr1 (see figure 7 ). fig 6. internal and external data memory structure 000h 2ffh 00h ffh upper 128 b internal ram lower 128 b internal ram (indirect and direct addressing) (indirect addressing) (direct addressing) special function registers (sfrs) 80h ffh ffffh 000h external data memory external data memory 2ffh 0000h extram = 0 extram = 1 expanded ram 0300h (indirect addressing) (indirect addressing) (indirect addressing) ffffh 80h 7fh 002aaa517 expanded ram 768 b P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 20 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.3 flash memory iap 6.3.1 flash organization the P89V51RB2/rc2/rd2 program memory consists of a 16/32/64 kb block. isp capability, in a second 8 kb block, is provided to allow the user code to be programmed in-circuit through the serial port. there are three methods of erasing or programming of the ?ash memory that may be used. first, the ?ash may be programmed or erased in the end-user application by calling low-level routines through a common entry point (iap). second, the on-chip isp bootloader may be invoked. this isp bootloader will, in turn, call low-level routines through the same common entry point that can be used by the end-user application. third, the ?ash may be programmed or erased using the parallel method by using a commercially available eprom programmer which supports this device. 6.3.2 boot block (block 1) when the microcontroller programs its own ?ash memory, all of the low level details are handled by code that is contained in block 1. a user program calls the common entry point in the block 1 with appropriate parameters to accomplish the desired operation. boot block operations include erase user code, program user code, program security bits, etc. fig 7. dual data pointer organization table 10. auxr1 - auxiliary register 1 (address a2h) bit allocation not bit addressable; reset value 00h bit 7 6 5 4 3 2 1 0 symbol - - - - gf2 0 - dps table 11. auxr1 - auxiliary register 1 (address a2h) bit description bit symbol description 7 to 4 - reserved for future use. should be set to 0 by user programs. 3 gf2 general purpose user-de?ned ?ag. 2 0 this bit contains a hard-wired 0. allows toggling of the dps bit by incrementing auxr1, without interfering with other bits in the register. 1 - reserved for future use. should be set to 0 by user programs. 0 dps data pointer select. chooses one of two data pointers for use by the program. see text for details. dpl 82h dps = 0 ? dptr0 dps = 1 ? dptr1 external data memory dps 002aaa518 dph 83h dptr0 dptr1 auxr1 / bit0 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 21 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core a chip-erase operation can be performed using a commercially available parallel programer. this operation will erase the contents of this boot block and it will be necessary for the user to reprogram this boot block (block 1) with the nxp-provided isp/iap code in order to use the isp or iap capabilities of this device. go to http://www .nxp .com/suppor t for questions or to obtain the hex ?le for this device. 6.3.3 isp isp is performed without removing the microcontroller from the system. the isp facility consists of a series of internal hardware resources coupled with internal ?rmware to facilitate remote programming of the P89V51RB2/rc2/rd2 through the serial port. this ?rmware is provided by nxp and embedded within each P89V51RB2/rc2/rd2 device. the nxp isp facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function uses ?ve pins (v dd , v ss , txd, rxd, and rst). only a small connector needs to be available to interface your application to an external circuit in order to use this feature. 6.3.4 using the isp the isp feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. it is also adaptable to a wide range of oscillator frequencies. this is accomplished by measuring the bit-time of a single bit in a received character. this information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. the isp feature requires that an initial character (an uppercase u) be sent to the P89V51RB2/rc2/rd2 to establish the baud rate. the isp ?rmware provides auto-echo of received characters. once baud rate initialization has been performed, the isp ?rmware will only accept intel hex-type records. intel hex records consist of ascii characters used to represent hexadecimal values and are summarized below: :nnaaaarrdd..ddcc P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 22 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core table 12. isp hex record formats record type command/data function 00 program user code memory :nnaaaa00dd..ddcc where: nn = number of bytes to program aaaa = address dd..dd = data bytes cc = checksum example: :100000000102030405006070809cc 01 end of file (eof), no operation :xxxxxx01cc where: xxxxxx = required ?eld but value is a dont care cc = checksum example: :00000001ff 02 set softice mode following the next reset the device will enter the softice mode. will erase user code memory, erase device serial number. :00000002cc where: xxxxxx = required ?eld but value is a dont care cc = checksum example: :00000002fe P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 23 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 03 miscellaneous write functions :nnxxxx03ffssddcc where: nn = number of bytes in the record xxxx = required ?eld but value is a dont care ff = subfunction code ss = selection code dd = data (if needed) cc = checksum subfunction code = 01 (erase block 0) ff=01 subfunction code = 05 (program security bit, double clock) ff=05 ss = 01 program security bit ss = 05 program double clock bit subfunction code = 08 (erase sector, 128 b) ff=08 ss = high byte of sector address (a15:8) dd = low byte of sector address (a7, a6:0 = 0) example: :0300000308e000f2 (erase sector at e000h) 04 display device data or blank check :05xxxx04sssseeeeffcc where 05 = number of bytes in the record xxxx = required ?eld but value is a dont care 04 = function code for display or blank check ssss = starting address, msb ?rst eeee = ending address, msb ?rst ff = subfunction 00 = display data 01 = blank check cc = checksum subfunction codes: example: :0500000400001fff00d9 (display from 0000h to 1fffh) table 12. isp hex record formats continued record type command/data function P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 24 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 05 miscellaneous read functions :02xxxx05ffsscc where: 02 = number of bytes in the record xxxx = required ?eld but value is a dont care 05 = function code for misc read ffss = subfunction and selection code 0000 = read manufacturer id 0001 = read device id 1 0002 = read bootcode version 0700 = read security bit (00 softice serial number match 0 sb 0 double clock) cc = checksum example: :020000050000f9 (display manufacturer id) 06 direct load of baud rate :02xxxx06hhllcc where: 02 = number of bytes in the record xxxx = required ?eld but value is a dont care hh = high byte of timer ll = low byte of timer cc = checksum example: :02000006ffffcc (load t2 = ffff) 07 reset serial number, erase user code, clear softice mode :xxxxxx07cc where: xxxxxx = required ?eld but value is a dont care 07 = reset serial number function cc = checksum example: :00000007f9 08 verify serial number :nnxxxx08ss..sscc where: xxxxxx = required ?eld but value is a dont care 08 = verify serial number function ss..ss = serial number contents cc = checksum example: :03000008010203ef (verify s/n = 010203) table 12. isp hex record formats continued record type command/data function P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 25 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.3.5 using the serial number this device has the option of storing a 31 b serial number along with the length of the serial number (for a total of 32 b) in a non-volatile memory space. when isp mode is entered, the serial number length is evaluated to determine if the serial number is in use. if the length of the serial number is programmed to either 00h or ffh, the serial number is considered not in use. if the serial number is in use, reading, programming, or erasing of the user code memory or the serial number is blocked until the user transmits a verify serial number record containing a serial number and length that matches the serial number and length previously stored in the device. the user can reset the serial number to all zeros and set the length to zero by sending the reset serial number' record. in addition, the reset serial number record will also erase all user code. 6.3.6 iap method several iap calls are available for use by an application program to permit selective erasing, reading and programming of ?ash sectors, security bit, con?guration bytes, and device id. all calls are made through a common interface, pgm_mtp. the programming functions are selected by setting up the microcontrollers registers before making a call to pgm_mtp at 1ff0h. the iap calls are shown in t ab le 13 . 09 write serial number :nnxxxx09ss..sscc where: xxxxxx = required ?eld but value is a dont care 09 = write serial number function ss..ss = serial number contents cc = checksum example: :03000009010203ee (write s/n = 010203) 0a display serial number :xxxxxx0acc where: xxxxxx = required ?eld but value is a dont care 0a = display serial number function cc = checksum example: :0000000af6 0b reset and run user code :xxxxxx0bcc where: xxxxxx = required ?eld but value is a dont care 0b = reset and run user code cc = checksum example: :0000000bf5 table 12. isp hex record formats continued record type command/data function P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 26 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core table 13. iap function calls iap function iap call parameters read id input parameters: r1 = 00h dph = 00h dpl = 00h = mfgr id dpl = 01h = device id 1 dpl = 02h = boot code version number return parameter(s): acc = requested parameter erase block 0 input parameters: r1 = 01h return parameter(s): acc = 00 = pass acc=!00=fail program user code input parameters: r1 = 02h dph = memory address msb dpl = memory address lsb acc = byte to program return parameter(s): acc = 00 = pass acc=!00=fail read user code input parameters: r1 = 03h dph = memory address msb dpl = memory address lsb return parameter(s): acc = device data P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 27 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.4 timers/counters 0 and 1 the two 16-bit timer/counter registers: timer 0 and timer 1 can be con?gured to operate either as timers or event counters (see t ab le 14 and t ab le 15 ). in the timer function, the register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of six oscillator periods, the count rate is 1 6 of the oscillator frequency. in the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t0 or t1. in this function, the external input is sampled once every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register in the machine cycle following the one in which the transition was detected. since it takes two machine cycles (12 oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is 1 12 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. in addition to the timer or counter selection, timer 0 and timer 1 have four operating modes from which to select. the timer or counter function is selected by control bits c/t in the special function register tmod. these two timer/counters have four operating modes, which are selected by bit-pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for both timers/counters. mode 3 is different. the four operating modes are described in the following text. program security bit, double clock input parameters: r1 = 05h dpl = 01h = security bit dpl = 05h = double clock return parameter(s): acc = 00 = pass acc=!00=fail read security bit, double clock, softice input parameters: acc = 07h return parameter(s): acc = 00 softice s/n-match 0 sb 0 dbl_clk erase sector input parameters: r1 = 08h dph = sector address high byte dpl = sector address low byte return parameter(s): acc = 00 = pass acc = !00 = fail table 13. iap function calls continued iap function iap call parameters P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 28 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core table 14. tmod - timer/counter mode control register (address 89h) bit allocation not bit addressable; reset value: 0000 0000b; reset source(s): any source bit 7 6 5 4 3 2 1 0 symbol t1gate t1c/ t t1m1 t1m0 t0gate t0c/ t t0m1 t0m0 table 15. tmod - timer/counter mode control register (address 89h) bit description bit symbol description t1/t0 bits controlling timer1/timer0 gate gating control when set. timer/counter x is enabled only while intx pin is high and trx control pin is set. when cleared, timer x is enabled whenever trx control bit is set. c/ t gating timer or counter selector cleared for timer operation (input from internal system clock.) set for counter operation (input from tx input pin). table 16. tmod - timer/counter mode control register (address 89h) m1/m0 operating mode m1 m0 operating mode 0 0 0 8048 timer tlx serves as 5-bit prescaler 0 1 1 16-bit timer/counter thx and tlx' are cascaded; there is no prescaler. 1 0 2 8-bit auto-reload timer/counter thx holds a value which is to be reloaded into tlx each time it over?ows. 1 1 3 (timer 0) tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. 1 1 3 (timer 1) timer/counter 1 stopped. table 17. tcon - timer/counter control register (address 88h) bit allocation bit addressable; reset value: 0000 0000b; reset source(s): any reset bit 7 6 5 4 3 2 1 0 symbol tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 table 18. tcon - timer/counter control register (address 88h) bit description bit symbol description 7 tf1 timer 1 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hardware when the processor vectors to timer 1 interrupt routine, or by software. 6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter 1 on/off. 5 tf0 timer 0 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hardware when the processor vectors to timer 0 interrupt routine, or by software. 4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter 0 on/off. 3 ie1 interrupt 1 edge ?ag. set by hardware when external interrupt 1 edge/low level is detected. cleared by hardware when the interrupt is processed, or by software. P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 29 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.4.1 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a ?xed divide-by-32 prescaler. figure 8 shows mode 0 operation. in this mode, the timer register is con?gured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt ?ag tfn. the count input is enabled to the timer when trn = 1 and either gate = 0 or intn = 1. (setting gate = 1 allows the timer to be controlled by external input intn, to facilitate pulse width measurements). trn is a control bit in the special function register tcon ( figure 7 ). the gate bit is in the tmod register. the 13-bit register consists of all 8 bits of thn and the lower 5 bits of tln. the upper 3 bits of tln are indeterminate and should be ignored. setting the run ?ag (trn) does not clear the registers. mode 0 operation is the same for timer 0 and timer 1 (see figure 8 ). there are two different gate bits, one for timer 1 (tmod.7) and one for timer 0 (tmod.3). 6.4.2 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register (thn and tln) are used. see figure 9 . 2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level that triggers external interrupt 1. 1 ie0 interrupt 0 edge ?ag. set by hardware when external interrupt 0 edge/low level is detected. cleared by hardware when the interrupt is processed, or by software. 0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level that triggers external interrupt 0. table 18. tcon - timer/counter control register (address 88h) bit description continued bit symbol description fig 8. timer/counter 0 or 1 in mode 0 (13-bit counter) 002aaa519 osc/6 tn pin trn tngate intn pin c/t = 0 c/t = 1 tln (5-bits) thn (8-bits) tfn control overflow interrupt P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 30 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.4.3 mode 2 mode 2 con?gures the timer register as an 8-bit counter (tln) with automatic reload, as shown in figure 10 . over?ow from tln not only sets tfn, but also reloads tln with the contents of thn, which must be preset by software. the reload leaves thn unchanged. mode 2 operation is the same for timer 0 and timer 1. 6.4.4 mode 3 when timer 1 is in mode 3 it is stopped (holds its count). the effect is the same as setting tr1=0. timer 0 in mode 3 establishes tl0 and th0 as two separate 8-bit counters. the logic for mode 3 and timer 0 is shown in figure 11 . tl0 uses the timer 0 control bits: t0c/ t, t0gate, tr0, int0, and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the timer 1 interrupt. mode 3 is provided for applications that require an extra 8-bit timer. with timer 0 in mode 3, the P89V51RB2/rc2/rd2 can look like it has an additional timer. note: when timer 0 is in mode 3, timer 1 can be turned on and off by switching it into and out of its own mode 3. it can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt. fig 9. timer/counter 0 or 1 in mode 1 (16-bit counter) 002aaa520 osc/6 tn pin trn tngate intn pin c/t = 0 c/t = 1 tln (8-bits) thn (8-bits) tfn control overflow interrupt fig 10. timer/counter 0 or 1 in mode 2 (8-bit auto-reload) 002aaa521 osc/6 tn pin trn tngate intn pin tln (8-bits) thn (8-bits) tfn control overflow reload interrupt c/t = 0 c/t = 1 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 31 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.5 timer 2 timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter, as selected by c/t2 in the special function register t2con. timer 2 has four operating modes: capture, auto-reload (up or down counting), clock-out, and baud rate generator which are selected according to t ab le 19 using t2con ( t ab le 20 and t ab le 21 ) and t2mod ( t ab le 22 and t ab le 23 ). fig 11. timer/counter 0 mode 3 (two 8-bit counters) 002aaa522 osc/2 tr1 tr0 tngate int0 pin tl0 (8-bits) tf0 control overflow interrupt th0 (8-bits) tf1 control overflow interrupt osc/6 t0 pin c/t = 0 c/t = 1 table 19. timer 2 operating mode rclk + tclk cp/ rl2 tr2 t2oe mode 0 0 1 0 16-bit auto reload 0 1 1 0 16-bit capture 0 0 1 1 programmable clock-out 1 x 1 0 baud rate generator x x 0 x off table 20. t2con - timer/counter 2 control register (address c8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 table 21. t2con - timer/counter 2 control register (address c8h) bit description bit symbol description 7 tf2 timer 2 over?ow ?ag set by a timer 2 over?ow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1 or when timer 2 is in clock-out mode. 6 exf2 timer 2 external ?ag is set when timer 2 is in capture, reload or baud-rate mode, exen2 = 1 and a negative transition on t2ex occurs. if timer 2 interrupt is enabled exf2 = 1 causes the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. 5 rclk receive clock ?ag. when set, causes the uart to use timer 2 over?ow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 over?ow to be used for the receive clock. P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 32 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.5.1 capture mode in the capture mode there are two options which are selected by bit exen2 in t2con. if exen2 = 0 timer 2 is a 16-bit timer or counter (as selected by c/ t2 in t2con) which upon over?owing sets bit tf2, the timer 2 over?ow bit. the capture mode is illustrated in figure 12 . 4 tclk transmit clock ?ag. when set, causes the uart to use timer 2 over?ow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 over?ows to be used for the transmit clock. 3 exen2 timer 2 external enable ?ag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. 2 tr2 start/stop control for timer 2. a logic 1 enables the timer to run. 1c/ t2 timer or counter select. (timer 2) 0 = internal timer (f osc / 6) 1 = external event counter (falling edge triggered; external clocks maximum rate = f osc / 12 0 cp/ rl2 capture/reload ?ag. when set, captures will occur on negative transitions at t2ex if exen2 = 1. when cleared, auto-reloads will occur either with timer 2 over?ows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 over?ow. table 22. t2mod - timer 2 mode control register (address c9h) bit allocation not bit addressable; reset value: xx00 0000b bit 7 6 5 4 3 2 1 0 symbol - - - - - - t2oe dcen table 23. t2mod - timer 2 mode control register (address c9h) bit description bit symbol description 7 to 2 - reserved for future use. should be set to 0 by user programs. 1 t2oe timer 2 output enable bit. used in programmable clock-out mode only. 0 dcen down count enable bit. when set, this allows timer 2 to be con?gured as an up/down counter. table 21. t2con - timer/counter 2 control register (address c8h) bit description continued bit symbol description P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 33 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core this bit can be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ien0 register). if exen2 = 1, timer 2 operates as described above, but with the added feature that a 1-to-0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2 like tf2 can generate an interrupt (which vectors to the same location as timer 2 over?ow interrupt). the timer 2 interrupt service routine can interrogate tf2 and exf2 to determine which event caused the interrupt. there is no reload value for tl2 and th2 in this mode. even when a capture event occurs from t2ex, the counter keeps on counting t2 pin transitions or f osc / 6 pulses. since once loaded contents of rcap2l and rcap2h registers are not protected, once timer2 interrupt is signalled it has to be serviced before new capture event on t2ex pin occurs. otherwise, the next falling edge on t2ex pin will initiate reload of the current value from tl2 and th2 to rcap2l and rcap2h and consequently corrupt their content related to previously reported interrupt. 6.5.2 auto-reload mode (up or down counter) in the 16-bit auto-reload mode, timer 2 can be con?gured as either a timer or counter (via c/ t2 in t2con), then programmed to count up or down. the counting direction is determined by bit dcen (down counter enable) which is located in the t2mod register (see t ab le 22 and t ab le 23 ). when reset is applied, dcen = 0 and timer 2 will default to counting up. if the dcen bit is set, timer 2 can count up or down depending on the value of the t2ex pin. figure 13 shows timer 2 counting up automatically (dcen = 0). fig 12. timer 2 in capture mode 002aaa523 osc ? 6 t2 pin c/t2 = 0 c/t2 = 1 tl2 (8-bits) th2 (8-bits) tf2 control capture tr2 timer 2 interrupt exf2 rcap2l rcap2h control exen2 transition detector t2ex pin P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 34 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core in this mode, there are two options selected by bit exen2 in t2con register. if exen2 = 0, then timer 2 counts up to 0ffffh and sets the tf2 (over?ow flag) bit upon over?ow. this causes the timer 2 registers to be reloaded with the 16-bit value in rcap2l and rcap2h. the values in rcap2l and rcap2h are preset by software means. auto reload frequency when timer 2 is counting up can be determined from this formula: (1) where supplyfrequency is either f osc (c/ t2 = 0) or frequency of signal on t2 pin (c/ t2 = 1). if exen2 = 1, a 16-bit reload can be triggered either by an over?ow or by a 1-to-0 transition at input t2ex. this transition also sets the exf2 bit. the timer 2 interrupt, if enabled, can be generated when either tf2 or exf2 is 1. microcontrollers hardware will need three consecutive machine cycles in order to recognize falling edge on t2ex and set exf2 = 1: in the ?rst machine cycle pin t2ex has to be sampled as 1; in the second machine cycle it has to be sampled as 0, and in the third machine cycle exf2 will be set to 1. in figure 14 , dcen = 1 and timer 2 is enabled to count up or down. this mode allows pin t2ex to control the direction of count. when a logic 1 is applied at pin t2ex timer 2 will count up. timer 2 will over?ow at 0ffffh and set the tf2 ?ag, which can then generate an interrupt, if the interrupt is enabled. this timer over?ow also causes the 16-bit value in rcap2l and rcap2h to be reloaded into the timer registers tl2 and th2. fig 13. timer 2 in auto-reload mode (dcen = 0) 002aaa524 osc ? 6 t2 pin c/t2 = 0 c/t2 = 1 tl2 (8-bits) th2 (8-bits) tf2 control reload tr2 timer 2 interrupt exf2 rcap2l rcap2h control exen2 transition detector t2ex pin supplyfrequency 65536 rcap2h rcap2l , () e () ------------------------------------------------------------------------------- - P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 35 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core when a logic 0 is applied at pin t2ex this causes timer 2 to count down. the timer will under?ow when tl2 and th2 become equal to the value stored in rcap2l and rcap2h. timer 2 under?ow sets the tf2 ?ag and causes 0ffffh to be reloaded into the timer registers tl2 and th2. the external ?ag exf2 toggles when timer 2 under?ows or over?ows. this exf2 bit can be used as a 17th bit of resolution if needed. 6.5.3 programmable clock-out a 50 % duty cycle clock can be programmed to come out on pin t2 (p1.0). this pin, besides being a regular i/o pin, has two additional functions. it can be programmed: 1. to input the external clock for timer/counter 2, or 2. to output a 50 % duty cycle clock ranging from 122 hz to 8 mhz at a 16 mhz operating frequency. to con?gure the timer/counter 2 as a clock generator, bit c/ t2 (in t2con) must be cleared and bit t2oe in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency depends on the oscillator frequency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in equation 2 : (2) where (rcap2h,rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. in the clock-out mode timer 2 roll-overs will not generate an interrupt. this is similar to when it is used as a baud-rate generator. 6.5.4 baud rate generator mode bits tclk and/or rclk in t2con allow the uart) transmit and receive baud rates to be derived from either timer 1 or timer 2 (see section 6.6 u ar ts on page 37 for details). when tclk = 0, timer 1 is used as the uart transmit baud rate generator. when fig 14. timer 2 in auto reload mode (dcen = 1) 002aaa525 tl2 (8-bits) th2 (8-bits) tf2 exf2 underflow timer 2 interrupt rcap2l rcap2h ffh ffh overflow (down-counting reload value) (up-counting reload value) count direction 1 = up 0 = down t2ex pin toggle osc ? 6 t2 pin c/t2 = 0 c/t2 = 1 control tr2 oscillatorfrequency 2 65536 rcap2h rcap2l , () e () ----------------------------------------------------------------------------------------- P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 36 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core tclk = 1, timer 2 is used as the uart transmit baud rate generator. rclk has the same effect for the uart receive baud rate. with these two bits, the serial port can have different receive and transmit baud rates C timer 1 or timer 2. figure 15 shows timer 2 in baud rate generator mode: the baud rate generation mode is like the auto-reload mode, when a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rates in modes 1 and 3 are determined by timer 2s over?ow rate given below: modes 1 and 3 baud rates = timer 2 over?ow rate / 16 the timer can be con?gured for either timer or counter operation. in many applications, it is con?gured for timer' operation (c/ t2 = 0). timer operation is different for timer 2 when it is being used as a baud rate generator. usually, as a timer it would increment every machine cycle (i.e., 1 6 the oscillator frequency). as a baud rate generator, it increments at the oscillator frequency. thus the baud rate formula is as follows: modes 1 and 3 baud rates = (3) n = 32 in x1 mode, 16 in x2 mode where: (rcap2h, rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. the timer 2 as a baud rate generator mode is valid only if rclk and/or tclk = 1 in t2con register. note that a rollover in th2 does not set tf2, and will not generate an interrupt. thus, the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. also if the exen2 (t2 external enable ?ag) is set, a 1-to-0 transition in t2ex (timer/counter 2 trigger input) will set exf2 (t2 external ?ag) but will fig 15. timer 2 in baud rate generator mode 002aaa526 tx/rx baud rate timer 2 interrupt osc ? 2 t2 pin c/t2 = 0 c/t2 = 1 tl2 (8-bits) th2 (8-bits) control tr2 exf2 rcap2l rcap2h control exen2 transition detector t2ex pin reload oscillatorfrequency n 65536 rcap2h rcap2l , () C () () ------------------------------------------------------------------------------------------------ P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 37 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core not cause a reload from (rcap2h, rcap2l) to (th2,tl2). therefore when timer 2 is in use as a baud rate generator, t2ex can be used as an additional external interrupt, if needed. when timer 2 is in the baud rate generator mode, one should not try to read or write th2 and tl2. under these conditions, a read or write of th2 or tl2 may not be accurate. the rcap2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. t ab le 24 shows commonly used baud rates and how they can be obtained from timer 2. 6.5.5 summary of baud rate equations timer 2 is in baud rate generating mode. if timer 2 is being clocked through pin t2 (p1.0) the baud rate is: baud rate = timer 2 over?ow rate / 16 if timer 2 is being clocked internally, the baud rate is: baud rate = f osc / (16 (65536 - (rcap2h, rcap2l))) where f osc = oscillator frequency to obtain the reload value for rcap2h and rcap2l, the above equation can be rewritten as: rcap2h, rcap2l = 65536 - f osc / (16 baud rate) 6.6 uarts the uart operates in all standard modes. enhancements over the standard 80c51 uart include framing error detection, and automatic address recognition. 6.6.1 mode 0 serial data enters and exits through rxd and txd outputs the shift clock. only 8 bits are transmitted or received, lsb ?rst. the baud rate is ?xed at 1 6 of the cpu clock frequency. uart con?gured to operate in this mode outputs serial clock on txd line no matter whether it sends or receives data on rxd line. table 24. timer 2 generated commonly used baud rates rate osc freq timer 2 rcap2h rcap2l 750 kbd 12 mhz ff ff 19.2 kbd 12 mhz ff d9 9.6 kbd 12 mhz ff b2 4.8 kbd 12 mhz ff 64 2.4 kbd 12 mhz fe c8 600 bd 12 mhz fb 1e 220 bd 12 mhz f2 af 600 bd 6 mhz fd 8f 220 bd 6 mhz f9 57 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 38 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.6.2 mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logical 0), 8 data bits (lsb ?rst), and a stop bit (logical 1). when data is received, the stop bit is stored in rb8 in special function register scon. the baud rate is variable and is determined by the timer 1 2 over?ow rate. 6.6.3 mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logical 0), 8 data bits (lsb ?rst), a programmable 9th data bit, and a stop bit (logical 1). when data is transmitted, the 9th data bit (tb8 in scon) can be assigned the value of 0 or (e.g. the parity bit (p, in the psw) could be moved into tb8). when data is received, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1 16 or 1 32 of the cpu clock frequency, as determined by the smod1 bit in pcon. 6.6.4 mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logical 0), 8 data bits (lsb ?rst), a programmable 9th data bit, and a stop bit (logical 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer 1 2 over?ow rate. table 25. scon - serial port control register (address 98h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol sm0/fe sm1 sm2 ren tb8 rb8 ti ri table 26. scon - serial port control register (address 98h) bit description bit symbol description 7 sm0/fe the usage of this bit is determined by smod0 in the pcon register. if smod0 = 0, this bit is sm0, which with sm1, de?nes the serial port mode. if smod0 = 1, this bit is fe (framing error). fe is set by the receiver when an invalid stop bit is detected. once set, this bit cannot be cleared by valid frames but can only be cleared by software. (note: it is recommended to set up uart mode bits sm0 and sm1 before setting smod0 to 1.) 6 sm1 with sm0, de?nes the serial port mode (see t ab le 27 below). 5 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then ri will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2 = 1 then ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be 0. 4 ren enables serial reception. set by software to enable reception. clear by software to disable reception. 3 tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 39 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.6.5 framing error framing error (fe) is reported in the scon.7 bit if smod0 (pcon.6) = 1. if smod0 = 0, scon.7 is the sm0 bit for the uart, it is recommended that sm0 is set up before smod0 is set to 1. 6.6.6 more about uart mode 1 reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset to align its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the ?rst bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the ?nal shift pulse is generated: (a) ri = 0, and (b) either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. 6.6.7 more about uart modes 2 and 3 reception is performed in the same manner as in mode 1. 2 rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is unde?ned. 1 ti transmit interrupt ?ag. set by hardware at the end of the 8th bit time in mode 0, or at the stop bit in the other modes, in any serial transmission. must be cleared by software. 0 ri receive interrupt ?ag. set by hardware at the end of the 8th bit time in mode 0, or approximately halfway through the stop bit time in all other modes. (see sm2 for exceptions). must be cleared by software. table 27. scon - serial port control register (address 98h) sm0/sm1 mode de?nition sm0, sm1 uart mode baud rate 0 0 0: shift register cpu clock / 6 0 1 1: 8-bit uart variable 1 0 2: 9-bit uart cpu clock / 32 or cpu clock / 16 1 1 3: 9-bit uart variable table 26. scon - serial port control register (address 98h) bit description continued bit symbol description P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 40 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the ?nal shift pulse is generated: (a) ri = 0, and (b) either sm2 = 0, or the received 9th data bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received 9th data bit goes into rb8, and the ?rst 8 data bits go into sbuf. 6.6.8 multiprocessor communications uart modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received or transmitted. when data is received, the 9th bit is stored in rb8. the uart can be programmed so that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. one way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it ?rst sends out an address byte which identi?es the target slave. an address byte differs from a data byte in a way that the 9th bit is 1 in an address byte and 0 in the data byte. with sm2 = 1, no slave will be interrupted by a data byte, i.e. the received 9th bit is 0. however, an address byte having the 9th bit set to 1 will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed or not. the addressed slave will clear its sm2 bit and prepare to receive the data (still 9 bits long) that follow. the slaves that werent being addressed leave their sm2 bits set and go on about their business, ignoring the subsequent data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit, although this is better done with the framing error ?ag. when uart receives data in mode 1 and sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 6.6.9 automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled for the uart by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt ?ag (ri) will be automatically set when the received byte contains either the given address or the broadcast' address. the 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to de?ne the slaves address, saddr, and the address mask, saden. saden is used to de?ne which bits in the saddr are to be used and which bits are dont care. the saden mask can be logically anded with the saddr to create the given address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. this device uses the methods presented in figure 16 to determine if a given or broadcast address has been received or not. P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 41 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core the following examples will help to show the versatility of this scheme. example 1, slave 0: (4) example 2, slave 1: (5) in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bi t0=0(forslave0)andbit1=0(forslave1). thus, both could be addressed with 1100 0000. fig 16. schemes used by the uart to detect given and broadcast addresses when multiprocessor communications is enabled 002aaa527 rx_byte(7) saddr(7) saden(7) rx_byte(0) saddr(0) . . . given_address_match logic used by uart to detect 'given address' in received data saddr(7) saden(7) rx_byte(7) saddr(0) saden(0) rx_byte(0) broadcast_address_match logic used by uart to detect 'given address' in received data saden(0) . . . saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 --------------------------------------------------- - saddr = 1100 0000 saden = 1111 1110 given = 1100 000x --------------------------------------------------- - P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 42 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: example 1, slave 0: (6) example 2, slave 1: (7) example 3, slave 2: (8) in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bi t1=0 and it can be uniquely addressed by 1110 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are treated as dont-cares. in most cases, interpreting the dont-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr and saden are loaded with 0s. this produces a given address of all dont cares as well as a broadcast address of all dont cares'. this effectively disables the automatic addressing mode and allows the microcontroller to use standard uart drivers which do not make use of this feature. 6.7 spi 6.7.1 spi features ? master or slave operation ? 10 mhz bit frequency (max) ? lsb ?rst or msb ?rst data transfer ? four programmable bit rates ? end of transmission (spif) ? write collision ?ag protection (wcol) ? wake-up from idle mode (slave mode only) 6.7.2 spi description the spi allows high-speed synchronous data transfer between the P89V51RB2/rc2/rd2 and peripheral devices or between several P89V51RB2/rc2/rd2 devices. figure 17 shows the correspondence between master and slave spi devices. the sck pin is the saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 --------------------------------------------------- - saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x --------------------------------------------------- - saddr = 1100 0000 saden = 1111 1100 given = 1100 00xx --------------------------------------------------- - P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 43 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core clock output and input for the master and slave modes, respectively. the spi clock generator will start following a write to the master devices spi data register. the written data is then shifted out of the mosi pin on the master device into the mosi pin of the slave device. following a complete transmission of one byte of data, the spi clock generator is stopped and the spif ?ag is set. an spi interrupt request will be generated if the spi interrupt enable bit (spie) and the serial port interrupt enable bit (es) are both set. an external master drives the slave select input pin, ss/p1[4], low to select the spi module as a slave. if ss/p1[4] has not been driven low, then the slave spi unit is not active and the mosi/p1[5] port can also be used as an input port pin. cpha and cpol control the phase and polarity of the spi clock. figure 18 and figure 19 show the four possible combinations of these two bits. fig 17. spi master-slave interconnection 002aaa528 8-bit shift register msb master lsb spi clock generator miso miso mosi mosi sck sck ss ss 8-bit shift register msb slave lsb v ss v dd table 28. spcr - spi control register (address d5h) bit allocation bit addressable; reset source(s): any reset; reset value: 0000 0000b bit 7 6 5 4 3 2 1 0 symbol spie spe dord mstr cpol cpha spr1 spr0 table 29. spcr - spi control register (address d5h) bit description bit symbol description 7 spie if both spie and es are set to one, spi interrupts are enabled. 6 spe spi enable bit. when set enables spi. 5 dord data transmission order. 0 = msb ?rst; 1 = lsb ?rst in data transmission. 4 mstr master/slave select. 1 = master mode, 0 = slave mode. 3 cpol clock polarity. 1 = sck is high when idle (active low), 0 = sck is low when idle (active high). P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 44 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 2 cpha clock phase control bit. 1 = shift triggered on the trailing edge of the clock; 0 = shift triggered on the leading edge of the clock. 1 spr1 spi clock rate select bit 1. along with spr0 controls the sck rate of the device when a master. spr1 and spr0 have no effect on the slave. see t ab le 30 below. 0 spr0 spi clock rate select bit 0. along with spr1 controls the sck rate of the device when a master. spr1 and spr0 have no effect on the slave. see t ab le 30 below. table 30. spcr - spi control register (address d5h) clock rate selection spr1 spr0 sck = f osc divided by 004 0116 1064 1 1 128 table 31. spsr - spi status register (address aah) bit allocation bit addressable; reset source(s): any reset; reset value: 0000 0000b bit 7 6 5 4 3 2 1 0 symbol spif wcol - - - - - - table 32. spsr - spi status register (address aah) bit description bit symbol description 7 spif spi interrupt ?ag. upon completion of data transfer, this bit is set to 1. if spie = 1 and es = 1, an interrupt is then generated. this bit is cleared by software. 6 wcol write collision flag. set if the spi data register is written to during data transfer. this bit is cleared by software. 5 to 0 - reserved for future use. should be set to 0 by user programs. table 29. spcr - spi control register (address d5h) bit description continued bit symbol description fig 18. spi transfer format with cpha = 0 002aaa529 sck cycle # (for reference) sck (cpol = 0) sck (cpol = 1) mosi (from master) miso (from slave) ss (to slave) 12345678 msb 654321lsb msb 654321lsb P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 45 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.8 watchdog timer the device offers a programmable watchdog timer (wdt) for fail safe protection against software deadlock and automatic recovery. to protect the system against software deadlock, the user software must refresh the wdt within a user-de?ned time period. if the software fails to do this periodical refresh, an internal hardware reset will be initiated if enabled (wdre = 1). the software can be designed such that the wdt times out if the program does not work properly. the wdt in the device uses the system clock (xtal1) as its time base. so strictly speaking, it is a watchdog counter rather than a wdt. the wdt register will increment every 344064 crystal clocks. the upper 8-bits of the time base register (wdtd) are used as the reload register of the wdt. the wdts ?ag bit is set by wdt over?ow and is not changed by wdt reset. user software can clear wdts by writing 1' to it. figure 20 provides a block diagram of the wdt. two sfrs (wdtc and wdtd) control wdt operation. during idle mode, wdt operation is temporarily suspended, and resumes upon an interrupt exit from idle. the time-out period of the wdt is calculated as follows: period = (255 - wdtd) 344064 1/f clk(xtal1) where wdtd is the value loaded into the wdtd register and f osc is the oscillator frequency. fig 19. spi transfer format with cpha = 1 002aaa530 msb sck cycle # (for reference) sck (cpol = 0) sck (cpol = 1) mosi (from master) miso (from slave) ss (to slave) 6 12345678 5 msb654321 lsb 4 3 2 1 lsb fig 20. block diagram of programmable wdt 002aaa531 wdt upper byte wdt reset internal reset 344064 clks clk (xtal1) external reset wdtc counter wdtd P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 46 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.9 pca the pca includes a special 16-bit timer that has ?ve 16-bit capture/compare modules associated with it. each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pwm. each module has a pin associated with it in port 1. module 0 is connected to p1.3 (cex0), module 1 to p1.4 (cex1), etc. registers ch and cl contain current value of the free running up counting 16-bit pca timer. the pca timer is a common time base for all ?ve modules and can be programmed to run at: 1 6 the oscillator frequency, 1 2 the oscillator frequency, the timer 0 over?ow, or the input on the eci pin (p1.2). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr (see t ab le 35 and t ab le 36 ). table 33. wdtc - watchdog control register (address coh) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - - wdout wdre wdts wdt swdt table 34. wdtc - watchdog control register (address coh) bit description bit symbol description 7 to 5 - reserved for future use. should be set to 0 by user programs. 4 wdout watchdog output enable. when this bit and wdre are both set, a watchdog reset will drive the reset pin active for 32 clocks. 3 wdre watchdog timer reset enable. when set enables a watchdog timer reset. 2 wdts watchdog timer reset ?ag, when set indicates that a wdt reset occurred. reset in software. 1 wdt watchdog timer refresh. set by software to force a wdt reset. 0 swdt start watchdog timer, when set starts the wdt. when cleared, stops the wdt. fig 21. pca module0 pca timer/counter p1.3/cex0 module1 p1.4/cex1 module2 p1.5/cex2 module3 p1.6/cex3 module4 p1.7/cex4 time base for pca modules module functions: - 16-bit capture - 16-bit timer - 16-bit high speed output - 8-bit pwm - watchdog timer (module 4 only) 16 bits 16 bits 002aaa532 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 47 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core in the cmod sfr there are three additional bits associated with the pca. they are cidl which allows the pca to stop during idle mode, wdte which enables or disables the watchdog function on module 4, and ecf which when set causes an interrupt and the pca over?ow ?ag cf (in the ccon sfr) to be set when the pca timer over?ows. the watchdog timer function is implemented in module 4 of pca. the ccon sfr contains the run control bit for the pca (cr) and the ?ags for the pca timer (cf) and each module (ccf4:0). to run the pca the cr bit (ccon.6) must be set by software. the pca is shut off by clearing this bit. the cf bit (ccon.7) is set when the pca counter over?ows and an interrupt will be generated if the ecf bit in the cmod register is set. the cf bit can only be cleared by software. bits 0 through 4 of the ccon register are the ?ags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these ?ags can only be cleared by software. all the modules share one interrupt vector. the pca interrupt system is shown in figure 22 . each module in the pca has a special function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. the registers contain the bits that control the mode that each module will operate in. the eccf bit (from ccapmn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the ccfn ?ag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module (see figure 22 ). pwm (ccapmn.1) enables the pulse width modulation mode. the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the modules capture/compare register. the match bit mat (ccapmn.3) when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the modules capture/compare register. the next two bits capn (ccapmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. the last bit in the register ecom (ccapmn.6) when set enables the comparator function. there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output. P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 48 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fig 22. pca interrupt system 002aaa533 pca timer/counter module0 cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 module1 module2 module3 module4 ecf eccfn ien0.6 ec ien0.7 ea ccapmn.0 cmod.0 ccon (d8h) to interrupt priority decoder table 35. cmod - pca counter mode register (address d9h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol cidl wdte - - - cps1 cps0 ecf table 36. cmod - pca counter mode register (address d9h) bit description bit symbol description 7 cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cidl = 1 programs it to be gated off during idle. 6 wdte watchdog timer enable: wdte = 0 disables watchdog timer function on module 4. wdte = 1 enables it. 5 to 3 - reserved for future use. should be set to 0 by user programs. 2 to 1 cps1, cps0 pca count pulse select (see t ab le 37 below). 0 ecf pca enable counter over?ow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ecf = 0 disables that function. table 37. cmod - pca counter mode register (address d9h) count pulse select cps1 cps0 select pca input 0 0 0 internal clock, f osc / 6 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 49 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 0 1 1 internal clock, f osc / 6 1 0 2 timer 0 over?ow 1 1 3 external clock at eci/p1.2 pin (max rate = f osc / 4) table 38. ccon - pca counter control register (address 0d8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 table 39. ccon - pca counter control register (address 0d8h) bit description bit symbol description 7 cf pca counter over?ow ?ag. set by hardware when the counter rolls over. cf ?ags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. 6 cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. 5 - reserved for future use. should be set to 0 by user programs. 4 ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 3 ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 2 ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 1 ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 0 ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. table 40. ccapmn - pca modules compare/capture register (address ccapm0 0dah, ccapm1 0dbh, ccapm2 0dch, ccapm3 0ddh, ccapm4 0deh) bit alloc. not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - ecomn cappn capnn matn togn pwmn eccfn table 41. ccapmn - pca modules compare/capture register (address ccapm0 0dah, ccapm1 0dbh, ccapm2 0dch, ccapm3 0ddh, ccapm4 0deh) bit desc. bit symbol description 7 - reserved for future use. should be set to 0 by user programs. 6 ecomn enable comparator. ecomn = 1 enables the comparator function. 5 cappn capture positive, cappn = 1 enables positive edge capture. 4 capnn capture negative, capnn = 1 enables negative edge capture. 3 matn match. when matn = 1 a match of the pca counter with this modules compare/capture register causes the ccfn bit in ccon to be set, ?agging an interrupt. table 37. cmod - pca counter mode register (address d9h) count pulse select continued cps1 cps0 select pca input P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 50 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.9.1 pca capture mode to use one of the pca modules in the capture mode ( figure 23 ) either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the modules capture registers (ccapnl and ccapnh). 2 togn toggle. when togn = 1, a match of the pca counter with this modules compare/capture register causes the cexn pin to toggle. 1 pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. 0 eccfn enable ccf interrupt. enables compare/capture ?ag ccfn in the ccon register to generate an interrupt. table 41. ccapmn - pca modules compare/capture register (address ccapm0 0dah, ccapm1 0dbh, ccapm2 0dch, ccapm3 0ddh, ccapm4 0deh) bit desc. bit symbol description table 42. pca module modes (ccapmn register) ecomn cappn capnn matn togn pwmn eccfn module function 0 0 0 0 0 0 0 no operation x 1 0 0 0 0 x 16-bit capture by a positive-edge trigger on cexn x 0 1 0 0 0 x 16-bit capture by a negative-edge trigger on cexn x 1 1 0 0 0 x 16-bit capture by any transition on cexn 1 0 0 1 0 0 x 16-bit software timer 1 0 0 1 1 0 x 16-bit high-speed output 1 0 0 0 0 1 0 8-bit pwm 1 0 0 1 x 0 x watchdog timer P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 51 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated. 6.9.2 16-bit software timer mode the pca modules can be used as software timers ( figure 24 ) by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the modules capture registers and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set. fig 23. pca capture mode 002aaa538 cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) pca interrupt pca timer/counter - ecomn 0 000 cappn capnn matn togn pwmn eccfn ccapmn, n = 0 to 4 (dah to deh) ch cl ccapnh ccapnl capture (to ccfn) cexn P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 52 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.9.3 high-speed output mode in this mode ( figure 25 ) the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the modules capture registers. to activate this mode the tog, mat, and ecom bits in the modules ccapmn sfr must be set. fig 24. pca compare mode 002aaa539 cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) pca interrupt - ecomn 00 100 cappn capnn matn togn pwmn eccfn ccapmn, n = 0 to 4 (dah to deh) 16-bit comparator pca timer/counter ch cl match (to ccfn) ccapnh ccapnl enable write to ccapnh write to ccapnl reset 01 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 53 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.9.4 pwm mode all of the pca modules can be used as pwm outputs ( figure 26 ). output frequency depends on the source for the pca timer. all of the modules will have the same frequency of output because they all share one and only pca timer. the duty cycle of each module is independently variable using the modules capture register ccapnl. when the value of the pca cl sfr is less than the fig 25. pca high-speed output mode 002aaa540 toggle cexn cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) pca interrupt - ecomn 00 100 cappn capnn matn togn pwmn eccfn ccapmn, n = 0 to 4 (dah to deh) 16-bit comparator pca timer/counter ch cl match (to ccfn) ccapnh ccapnl enable write to ccapnh write to ccapnl reset 01 fig 26. pca pwm mode 002aaa541 - ecomn 0 1 0 001 1 cappn capnn matn togn pwmn eccfn ccapmn, n = 0 to 4 (dah to deh) ccapnl 8-bit comparator pca timer/counter ccapnh cl enable cexn cl < ccapnl cl 3 ccapnl 0 1 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 54 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core value in the modules ccapnl sfr the output will be low, when it is equal to or greater than the output will be high. when cl over?ows from ff to 00, ccapnl is reloaded with the value in ccapnh. this allows updating the pwm without glitches. the pwm and ecom bits in the modules ccapmn register must be set to enable the pwm mode. 6.9.5 pca watchdog timer an on-board watchdog timer is available with the pca to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 26 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven high. users software then must periodically change (ccap4h,ccap4l) to keep a match from occurring with the pca timer (ch,cl). this code is given in the watchdog routine shown above. in order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the pca timer. 2. periodically change the pca timer value so it will never match the compare values. 3. disable the watchdog by clearing the wdte bit before a match occurs and then re-enable it. the ?rst two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second option is also not recommended if other pca modules are being used. remember, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most applications the ?rst solution is the best option. ;call the following watchdog subroutine periodically. clr ea ;hold off interrupts mov ccap4l,#00 ;next compare value is within 255 counts of current pca timer value mov ccap4h,ch setb ea ;re-enable interrupts ret this routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an in?nite loop, interrupts will still be serviced and the watchdog will keep getting reset. thus, the purpose of the watchdog would be defeated. instead, call this subroutine from the main program within 2 16 count of the pca timer. P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 55 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.10 security bit the security bit protects against software piracy and prevents the contents of the ?ash from being read by unauthorized parties in parallel programmer mode. it also protects against code corruption resulting from accidental erasing and programming to the internal ?ash memory. when the security bit is activated all parallel programming commands except for chip-erase are ignored (thus the device cannot be read). however, isp reading, writing, or erasing of the users code can still be performed if the serial number and length has not been programmed. therefore, when a user requests to program the security bit, the programmer should prompt the user and program a serial number into the device. 6.11 interrupt priority and polling sequence the device supports eight interrupt sources under a four level priority scheme. t ab le 43 summarizes the polling sequence of the supported interrupts. note that the spi serial interface and the uart share the same interrupt vector. (see figure 27 ). table 43. interrupt polling sequence description interrupt ?ag vector address interrupt enable interrupt priority service priority wake-up power-down ext. int0 ie0 0003h ex0 px0/h 1 (highest) yes brownout - 004bh ebo pbo/h 2 no t0 tf0 000bh et0 pt0/h 3 no ext. int1 ie1 0013h ex1 px1/h 4 yes t1 tf1 001bh et1 pt1/h 5 no pca cf/ccfn 0033h ec ppch 6 no uart/spi ti/ri/spif 0023h es ps/h 7 no t2 tf2, exf2 002bh et2 pt2/h 8 no P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 56 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fig 27. interrupt structure 002aaa544 highest priority interrupt interrupt polling sequence int0# ie and iea registers ip/iph/ipa/ipah registers individual enables global disable ie0 0 1 it0 lowest priority interrupt tf0 brownout int1# tf1 cf ecf ccfn eccfn tf2 exf2 ie1 0 1 it1 spif spie ri ti table 44. ien0 - interrupt enable register 0 (address a8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol ea ec et2 es et1 ex1 et0 ex0 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 57 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core table 45. ien0 - interrupt enable register 0 (address a8h) bit description bit symbol description 7 ea interrupt enable bit: ea = 1 interrupt(s) can be serviced, ea = 0 interrupt servicing disabled. 6 ec pca interrupt enable bit. 5 et2 timer 2 interrupt enable. 4 es serial port interrupt enable. 3 et1 timer 1 over?ow interrupt enable. 2 ex1 external interrupt 1 enable. 1 et0 timer 0 over?ow interrupt enable. 0 ex0 external interrupt 0 enable. table 46. ien1 - interrupt enable register 1 (address e8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - - - ebo - - - table 47. ien1 - interrupt enable register 1 (address e8h) bit description bit symbol description 7 to 4 - reserved for future use. should be set to 0 by user programs. 3 ebo brownout interrupt enable. 1 = enable, 0 = disable. 2 to 0 - reserved for future use. should be set to 0 by user programs. table 48. ip0 - interrupt priority 0 low register (address b8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - ppc pt2 ps pt1 px1 pt0 px0 table 49. ip0 - interrupt priority 0 low register (address b8h) bit description bit symbol description 7 - reserved for future use. should be set to 0 by user programs. 6 ppc pca interrupt priority low bit. 5 pt2 timer 2 interrupt priority low bit. 4 ps serial port interrupt priority low bit. 3 pt1 timer 1 interrupt priority low bit. 2 px1 external interrupt 1 priority low bit. 1 pt0 timer 0 interrupt priority low bit. 0 px0 external interrupt 0 priority low bit. table 50. ip0h - interrupt priority 0 high register (address b7h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - ppch pt2h psh pt1h px1h pt0h px0h P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 58 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.12 power-saving modes the device provides two power saving modes of operation for applications where power consumption is critical. the two modes are idle and power-down, see t ab le 56 . 6.12.1 idle mode idle mode is entered setting the idl bit in the pcon register. in idle mode, the program counter (pc) is stopped. the system clock continues to run and all interrupts and peripherals remain active. the on-chip ram and the special function registers hold their data during this mode. table 51. ip0h - interrupt priority 0 high register (address b7h) bit description bit symbol description 7 - reserved for future use. should be set to 0 by user programs. 6 ppch pca interrupt priority high bit. 5 pt2h timer 2 interrupt priority high bit. 4 psh serial port interrupt priority high bit. 3 pt1h timer 1 interrupt priority high bit. 2 px1h external interrupt 1 priority high bit. 1 pt0h timer 0 interrupt priority high bit. 0 px0h external interrupt 0 priority high bit. table 52. ip1 - interrupt priority 1 register (address f8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - - pbo - - - - table 53. ip1 - interrupt priority 1 register (address f8h) bit description bit symbol description 7 to 5 - reserved for future use. should be set to 0 by user programs. 4 pbo brownout interrupt priority bit. 3 to 0 - reserved for future use. should be set to 0 by user programs. table 54. ip1h - interrupt priority 1 high register (address f7h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - - pboh - - - - table 55. ip1h - interrupt priority 1 high register (address f7h) bit description bit symbol description 7 to 5 - reserved for future use. should be set to 0 by user programs. 4 pboh brownout interrupt priority bit. 3 to 0 - reserved for future use. should be set to 0 by user programs. P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 59 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core the device exits idle mode through either a system interrupt or a hardware reset. exiting idle mode via system interrupt, the start of the interrupt clears the idl bit and exits idle mode. after exit the interrupt service routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the idle mode. a hardware reset starts the device similar to a power-on reset. 6.12.2 power-down mode the power-down mode is entered by setting the pd bit in the pcon register. in the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. sram contents are retained during power-down, the minimum v dd level is 2.0 v. the device exits power-down mode through either an enabled external level sensitive interrupt or a hardware reset. the start of the interrupt clears the pd bit and exits power-down. holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. upon interrupt signal restored to logic v ih , the interrupt service routine program execution resumes beginning at the instruction immediately following the instruction which invoked power-down mode. a hardware reset starts the device similar to power-on reset. to exit properly out of power-down mode, the reset or external interrupt should not be executed before the v dd line is restored to its normal operating voltage. be sure to hold v dd voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). table 56. power-saving modes mode initiated by state of mcu exited by idle mode software (set idl bit in pcon) mov pcon, #01h clk is running. interrupts, serial port and timers/counters are active. program counter is stopped. ale and psen signals at a high level during idle. all registers remain unchanged. enabled interrupt or hardware reset. start of interrupt clears idl bit and exits idle mode, after the isr reti instruction, program resumes execution beginning at the instruction following the one that invoked idle mode. a user could consider placing two or three nop instructions after the instruction that invokes idle mode to eliminate any problems. a hardware reset restarts the device similar to a power-on reset. power-down mode software (set pd bit in pcon) mov pcon, #02h clk is stopped. on-chip sram and sfr data is maintained. ale and psen signals at a low level during power -down. external interrupts are only active for level sensitive interrupts, if enabled. enabled external level sensitive interrupt or hardware reset. start of interrupt clears pd bit and exits power-down mode, after the isr reti instruction program resumes execution beginning at the instruction following the one that invoked power-down mode. a user could consider placing two or three nop instructions after the instruction that invokes power-down mode to eliminate any problems. a hardware reset restarts the device similar to a power-on reset. P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 60 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 6.13 system clock and clock options 6.13.1 clock input options and recommended capacitor values for oscillator shown in figure 28 and figure 29 are the input and output of an internal inverting ampli?er (xtal1, xtal2), which can be con?gured for use as an on-chip oscillator. when driving the device from an external clock source, xtal2 should be left disconnected and xtal1 should be driven. at start-up, the external oscillator may encounter a higher capacitive load at xtal1 due to interaction between the ampli?er and its feedback capacitance. however, the capacitance will not exceed 15 pf once the external signal meets the v il and v ih speci?cations. crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one application to another. c1 and c2 should be adjusted appropriately for each design. t ab le 57 shows the typical values for c1 and c2 vs. crystal type for various frequencies. more speci?c information about on-chip oscillator design can be found in the flashflex51 oscillator circuit design considerations application note. 6.13.2 clock doubling option by default, the device runs at 12 clocks per machine cycle (x1 mode). the device has a clock doubling option to speed up to 6 clocks per machine cycle (please see t ab le 58 ). clock double mode can be enabled either by an external programmer or using iap. when set, the edc bit in fst register will indicate 6-clock mode. the clock double mode is only for doubling the internal system clock and the internal ?ash memory, i.e. ea = 1. to access the external memory and the peripheral devices, careful consideration must be taken. also note that the crystal output (xtal2) will not be doubled. table 57. recommended values for c1 and c2 by crystal type crystal c1=c2 quartz 20 pf to 30 pf ceramic 40 pf to 50 pf fig 28. oscillator characteristics (using the on-chip oscillator) 002aaa545 xtal2 xtal1 v ss c 1 c 2 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 61 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fig 29. oscillator characteristics (external clock drive) table 58. clock doubling features device standard mode (x1) clock double mode (x2) clocks per machine cycle max. external clock frequency (mhz) clocks per machine cycle max. external clock frequency (mhz) p89v51rd2 12 40 6 20 table 59. fst - flash status register (address b6) bit allocation not bit addressable; reset value: xxxx x0xxb bit 7 6 5 4 3 2 1 0 symbol - sb - - edc - - - table 60. fst - flash status register (address b6) bit description bit symbol description 7 - reserved for future use. should be set to 0 by user programs. 6 sb security bit. 5 to 4 - reserved for future use. should be set to 0 by user programs. 3 edc enable double clock. 2 to 0 - reserved for future use. should be set to 0 by user programs. 002aaa546 xtal2 n.c. xtal1 external oscillator signal v ss P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 62 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 7. limiting values 8. static characteristics table 61. limiting values in accordance with the absolute maximum rating system (iec 60134). parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. symbol parameter conditions min max unit t amb(bias) bias ambient temperature - 55 +125 c t stg storage temperature - 65 +150 c v i input voltage on ea pin to v ss - 0.5 +14 v v n voltage on any other pin except v ss ; with respect to v dd - 0.5 v dd + 0.5 v i ol(i/o) low-level output current per input/output pin pins p1.5, p1.6, p1.7 - 20 ma all other pins - 15 ma p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w table 62. static characteristics t a =0 c to +70 c or - 40 cto+85 c; v dd = 4.5 v to 5.5 v; v ss =0v symbol parameter conditions min typ max unit n endu(?) endurance of ?ash memory jedec standard a117 [1] 10000 - - cycles t ret(?) ?ash memory retention time jedec standard a103 [1] 100 - - years i latch i/o latch-up current jedec standard 78 [1] 100 + i dd -- ma v th(hl) high-low threshold voltage 4.5 v < v dd < 5.5 v - 0.5 - 0.2v dd - 0.1 v v th(lh) low-high threshold voltage except xtal1, rst 0.2v dd + 0.9 - v dd + 0.5 v v ih high-level input voltage 4.5 v < v dd < 5.5 v; xtal1, rst 0.7v dd - 6.0 v v ol low-level output voltage v dd = 4.5 v; ports 1, 2, 3, except psen, ale [2] [3] [4] i ol = 100 m a - - 0.3 v i ol = 1.6 ma - - 0.45 v i ol = 3.5 ma - - 1.0 v v dd = 4.5 v; port 0, psen, ale i ol = 200 m a - - 0.3 v i ol = 3.2 ma - - 0.45 v P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 63 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core [1] this parameter is measured only for initial quali?cation and after a design or process change that could affect this paramet er. [2] under steady state (non-transient) conditions, i ol must be externally limited as follows: a) maximum i ol per 8-bit port: 26 ma b) maximum i ol total for all outputs: 71 ma c) if i ol exceeds the test condition, v oh may exceed the related speci?cation. pins are not guaranteed to sink current greater than the listed test conditions. [3] capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol of ale and ports 1 and 3. the noise due to external bus capacitance discharging into the port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. in the worst cases (capacitive loading > 100 pf), the noise pulse on the ale pin may exceed 0.8 v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. [4] load capacitance for port 0, ale and psen = 100 pf, load capacitance for all other outputs = 80 pf. [5] capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the v dd - 0.7 v speci?cation when the address bits are stabilizing. [6] pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curre nt reaches its maximum value when v i is approximately 2 v. [7] pin capacitance is characterized but not tested. ea = 25 pf (max). v oh high-level output voltage v dd = 4.5 v; ports 1, 2, 3, ale, psen [5] i oh = - 10 m av dd - 0.3 - - v i oh = - 30 m av dd - 0.7 - - v i oh = - 60 m av dd - 1.5 - - v v dd = 4.5 v; port 0 in external bus mode i oh = - 200 m av dd - 0.3 - - v i oh = - 3.2 ma v dd - 0.7 - - v v bo brownout trip voltage 3.85 - 4.15 v i il low-level input current v i = 0.4 v; ports 1, 2, 3 - - - 75 m a i thl high-low transition current v i = 2 v; ports 1, 2, 3 [6] -- - 650 m a i li input leakage current 0.45 v < v i P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 65 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 9. dynamic characteristics [1] t cy(clk) = 1 / f osc . [2] calculated values are for 6-clock mode only. table 63. dynamic characteristics over operating conditions: load capacitance for port 0, ale, and psen = 100 pf; load capacitance for all other outputs = 80 pf t a =0 c to +70 c or - 40 cto+85 c; v dd = 4.5 v to 5.5 v; v ss =0v [1] [2] symbol parameter conditions min typ max unit f osc oscillator frequency x1 mode 0 - 40 mhz x2 mode 0 - 20 mhz iap 0.25 - 40 mhz t lhll ale pulse width 2t cy(clk) - 15 - - ns t avll address valid to ale low time t cy(clk) - 15 - - ns t llax address hold after ale low time t cy(clk) - 15 - - ns t lliv ale low to valid instruction in time - - 4t cy(clk) - 45 ns t llpl ale low to psen low time t cy(clk) - 15 - - ns t plph psen pulse width 3t cy(clk) - 15 - - ns t pliv psen low to valid instruction in time - - 3t cy(clk) - 50 ns t pxix input instruction hold after psen time 0 - - ns t pxiz input instruction ?oat after psen time - - t cy(clk) - 15 ns t pxav psen to address valid time t cy(clk) - 8- - ns t aviv address to valid instruction in time - - 5t cy(clk) - 60 ns t plaz psen low to address ?oat time - - 10 ns t rlrh rd low pulse width 6t cy(clk) - 30 - - ns t wlwh wr low pulse width 6t cy(clk) - 30 - - ns t rldv rd low to valid data in time - - 5t cy(clk) - 50 ns t rhdx data hold after rd time 0 - - ns t rhdz data ?oat after rd time - - 2t cy(clk) - 12 ns t lldv ale low to valid data in time - - 8t cy(clk) - 50 ns t avdv address to valid data in time - - 9t cy(clk) - 75 ns t llwl ale low to rd or wr low time 3t cy(clk) - 15 - 3t cy(clk) + 15 ns t avwl address to rd or wr low time 4t cy(clk) - 30 - - ns t whqx data hold after wr time t cy(clk) - 20 - - ns t qvwh data output valid to wr high time 7t cy(clk) - 50 - - ns t rlaz rd low to address ?oat time - - 0 ns t whlh rd or wr high to ale high time t cy(clk) - 15 - t cy(clk) + 15 ns P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 66 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 9.1 explanation of symbols each timing symbol has 5 characters. the ?rst character is always a t (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a address c clock d input data h logic level high i instruction (program memory contents) l logic level low or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z high impedance (float) example: t avll = address valid to ale low time t llpl = ale low to psen low time fig 31. external program memory read cycle 002aaa548 port 2 psen ale a0 to a7 t llax t plaz t pxiz t llpl t aviv t avll t lliv t pliv t plph instr in a8 to a15 a8 to a15 a0 to a7 port 0 t pxix t pxav t lhll P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 67 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fig 32. external data memory read cycle ale psen port 0 port 2 rd a0 to a7 from ri to dpl data in a0 to a7 from pcl instr in p2[0] to p2[7] or a8 to a15 from dpf a0 to a15 from pch t lldv 002aaa549 t whlh t avdv t llwl t avll t avwl t rlrh t rldv t llax t rhdz t rhdx t rlaz fig 33. external data memory write cycle 002aaa550 port 2 port 0 wr psen ale t lhll p2[7:0] or a8 to a15 from dph a0 to a7 from ri or dpl data out instr in t avll t avwl t llwl t llax t wlwh t qvwh t whqx t whlh a8 to a15 from pch a0 to a7 from pcl P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 68 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core table 64. external clock drive symbol parameter oscillator unit 40 mhz variable min max min max f osc oscillator frequency - - 0 40 mhz t cy(clk) clock cycle time 25 - - - ns t chcx clock high time 8.75 - 0.35t cy(clk) 0.65t cy(clk) ns t clcx clock low time 8.75 - 0.35t cy(clk) 0.65t cy(clk) ns t clch clock rise time - 10 - - ns t chcl clock fall time - 10 - - ns fig 34. external clock drive waveform t chcl t clcx t chcx t cy(clk) t clch 002aaa907 0.2v dd + 0.9 v 0.2v dd - 0.1 v v dd - 0.5 v 0.45 v table 65. serial port timing symbol parameter oscillator unit 40 mhz variable min max min max t xlxl serial port clock cycle time 0.3 - 12t cy(clk) - m s t qvxh output data set-up to clock rising edge time 117 - 10t cy(clk) - 133 - ns t xhqx output data hold after clock rising edge time 0- 2t cy(clk) - 50 - ns t xhdx input data hold after clock rising edge time 0- 0 - ns t xhdv input data valid to clock rising edge time - 117 - 10t cy(clk) - 133 ns P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 69 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fig 35. shift register mode timing waveforms 002aaa552 ale 0 instruction 1 2 3 4 5 6 7 8 01234567 valid valid valid valid valid valid valid valid t xlxl set ti set ri t xhqx t qvxh t xhdv t xhdx clock output data write to sbuf input data clear ri table 66. spi interface timing symbol parameter conditions variable clock f osc =18mhz unit min max min max f spi spi operating frequency 0 t cy(clk) / 4 0 10 mhz t spicyc spi cycle time see figure 36 , 37 , 38 , 39 4t cy(clk) - 222 - ns t spilead spi enable lead time see figure 38 , 39 250 - 250 - ns t spilag spi enable lag time see figure 38 , 39 250 - 250 - ns t spiclkh spiclk high time see figure 36 , 37 , 38 , 39 2t cy(clk) - 111 - ns t spiclkl spiclk low time see figure 36 , 37 , 38 , 39 2t cy(clk) - 111 - ns t spidsu spi data set-up time master or slave; see figure 36 , 37 , 38 , 39 100 - 100 - ns t spidh spi data hold time master or slave; see figure 36 , 37 , 38 , 39 100 - 100 - ns t spia spi access time see figure 38 , 39 0 80 0 80 ns t spidis spi disable time see figure 38 , 39 0 160 - 160 ns t spidv spi enable to output data valid time see figure 36 , 37 , 38 , 39 - 111 - 111 ns t spioh spi output data hold time see figure 36 , 37 , 38 , 39 0-0-ns t spir spi rise time see figure 36 , 37 , 38 , 39 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns t spif spi fall time see figure 36 , 37 , 38 , 39 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 70 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fig 36. spi master timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spir t spidv t spif t spir t spif t spir ss spiclk (cpol = 0) (output) 002aaa908 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in fig 37. spi master timing (cpha = 1) t spicyc t spiclkl t spiclkl t spiclkh t spiclkh master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spidv t spir t spidv t spif t spif t spir t spir ss spiclk (cpol = 0) (output) 002aaa909 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 71 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fig 38. spi slave timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl t spilead t spilag t spidsu t spidh t spidh t spidsu t spidsu t spir t spia t spioh t spidis t spir slave msb/lsb out msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spioh t spidv t spir t spir t spif t spif ss spiclk (cpol = 0) (input) 002aaa910 spiclk (cpol = 1) (input) miso (output) mosi (input) not defined fig 39. spi slave timing (cpha = 1) 002aaa911 t spicyc t spiclkh t spiclkh t spiclkl t spilead t spiclkl t spilag t spidsu t spidsu t spidsu t spidh t spidh t spir t spir t spir t spia t spioh t spioh t spioh t spidis slave msb/lsb out not defined msb/lsb in lsb/msb in slave lsb/msb out t spidv t spidv t spidv t spir t spif t spif ss spiclk (cpol = 0) (input) spiclk (cpol = 1) (input) miso (output) mosi (input) P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 72 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fig 40. test load example all other pins disconnected fig 41. i dd test condition, active mode all other pins disconnected fig 42. i dd test condition, idle mode 002aaa555 to dut to tester c l 002aaa556 v dd v dd v dd p0 ea rst xtal2 (n.c.) clock signal xtal1 v ss i dd v dd 8 002aaa557 v dd v dd v dd p0 ea rst xtal2 (n.c.) clock signal xtal1 v ss i dd 8 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 73 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core all other pins disconnected fig 43. i dd test condition, power-down mode 002aaa558 v dd v dd = 2 v v dd p0 ea rst xtal2 (n.c.) xtal1 v ss i dd v dd 8 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 74 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 10. package outline fig 44. sot129-1 (dip40) package outline unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot129-1 99-12-27 03-02-13 a min. a max. b z max. w m e e 1 1.70 1.14 0.53 0.38 0.36 0.23 52.5 51.5 14.1 13.7 3.60 3.05 0.254 2.54 15.24 15.80 15.24 17.42 15.90 2.25 4.7 0.51 4 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 0.56 0.54 0.14 0.12 0.01 0.1 0.6 0.62 0.60 0.69 0.63 0.089 0.19 0.02 0.16 051g08 mo-015 sc-511-40 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 40 1 21 20 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1) (1) (1) dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1 P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 75 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fig 45. sot376-1 (tqfp44) package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.45 0.30 0.18 0.12 10.1 9.9 0.8 12.15 11.85 1.2 0.8 7 0 o o 0.2 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot376-1 137e08 ms-026 00-01-19 02-03-14 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.2 0.8 d b p e e b 11 d h b p e h v m b d z d a z e e v m a 1 44 34 33 23 22 12 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale tqfp44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm sot376-1 pin 1 index P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 76 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core fig 46. sot187-2 (plcc44) package outline unit a a 1 min. a 4 max. b p ey w v b references outline version european projection issue date iec jedec jeita mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 2.16 45 o 0.18 0.1 0.18 dimensions (mm dimensions are derived from the original inch dimensions) note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. sot187-2 d (1) e (1) 16.66 16.51 h d h e 17.65 17.40 z d (1) max. z e (1) max. 2.16 b 1 0.81 0.66 k 1.22 1.07 0.180 0.165 0.02 0.12 a 3 0.25 0.01 0.656 0.650 0.05 0.695 0.685 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 e d e e 16.00 14.99 0.63 0.59 16.00 14.99 0.63 0.59 0.085 0.032 0.026 0.048 0.042 29 39 44 1 6 717 28 18 40 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k x y e e b d h e e e h v m b d z d a z e e v m a pin 1 index 112e10 ms-018 edr-7319 0 5 10 mm scale 99-12-27 01-11-14 inches plcc44: plastic leaded chip carrier; 44 leads sot187-2 d e P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 77 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 11. abbreviations table 67. abbreviations acronym description emi electro-magnetic interference iap in-application programming isp in-system programming mcu microcontroller unit pca programmable counter array pwm pulse width modulator rc resistance-capacitance sfr special function register spi serial peripheral interface ttl transistor-transistor logic uart universal asynchronous receiver/transmitter P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 78 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 12. revision history table 68. revision history document id release date data sheet status change notice supersedes P89V51RB2_rc2_rd2_4 20070501 product data sheet - P89V51RB2_rc2_rd2-03 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where applicable. ? added new part types P89V51RB2fa, P89V51RB2fn, p89v51rc2fn, and p89v51rd2fn; removed part types P89V51RB2ba and p89v51rc2bn. P89V51RB2_rc2_rd2-03 20041202 product data - P89V51RB2_rc2_rd2-02 p89v51rd2-02 20041011 product data - p89v51rd2-01 p89v51rd2-01 20040301 product data - - P89V51RB2_rc2_rd2_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 1 may 2007 79 of 80 nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core 13. legal information 13.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 13.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 13.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 13.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 14. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation. nxp semiconductors P89V51RB2/rc2/rd2 8-bit microcontrollers with 80c51 core ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 1 may 2007 document identifier: P89V51RB2_rc2_rd2_4 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 15. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 functional description . . . . . . . . . . . . . . . . . . 10 6.1 special function registers . . . . . . . . . . . . . . . . 10 6.2 memory organization . . . . . . . . . . . . . . . . . . . 14 6.2.1 flash program memory bank selection. . . . . . 14 6.2.2 power-on reset code execution. . . . . . . . . . . . 14 6.2.3 software reset. . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2.4 brownout detect reset. . . . . . . . . . . . . . . . . . . 15 6.2.5 watchdog reset. . . . . . . . . . . . . . . . . . . . . . . . 16 6.2.6 data ram memory . . . . . . . . . . . . . . . . . . . . . 16 6.2.7 expanded data ram addressing . . . . . . . . . . 16 6.2.8 dual data pointers. . . . . . . . . . . . . . . . . . . . . . 19 6.3 flash memory iap . . . . . . . . . . . . . . . . . . . . . 20 6.3.1 flash organization . . . . . . . . . . . . . . . . . . . . . 20 6.3.2 boot block (block 1) . . . . . . . . . . . . . . . . . . . . 20 6.3.3 isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3.4 using the isp . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3.5 using the serial number . . . . . . . . . . . . . . . . . 25 6.3.6 iap method . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 27 6.4.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.5 timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.5.1 capture mode . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.5.2 auto-reload mode (up or down counter) . . . . . 33 6.5.3 programmable clock-out . . . . . . . . . . . . . . . . . 35 6.5.4 baud rate generator mode . . . . . . . . . . . . . . . 35 6.5.5 summary of baud rate equations . . . . . . . . . . 37 6.6 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.6.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.6.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6.5 framing error . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.6.6 more about uart mode 1 . . . . . . . . . . . . . . . 39 6.6.7 more about uart modes 2 and 3 . . . . . . . . . 39 6.6.8 multiprocessor communications . . . . . . . . . . . 40 6.6.9 automatic address recognition . . . . . . . . . . . . 40 6.7 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.7.1 spi features . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.7.2 spi description . . . . . . . . . . . . . . . . . . . . . . . . 42 6.8 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 45 6.9 pca . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.9.1 pca capture mode. . . . . . . . . . . . . . . . . . . . . 50 6.9.2 16-bit software timer mode. . . . . . . . . . . . . . . 51 6.9.3 high-speed output mode . . . . . . . . . . . . . . . . 52 6.9.4 pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.9.5 pca watchdog timer . . . . . . . . . . . . . . . . . . . 54 6.10 security bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.11 interrupt priority and polling sequence . . . . . . 55 6.12 power-saving modes . . . . . . . . . . . . . . . . . . . 58 6.12.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.12.2 power-down mode . . . . . . . . . . . . . . . . . . . . . 59 6.13 system clock and clock options . . . . . . . . . . . 60 6.13.1 clock input options and recommended capacitor values for oscillator . . . . . . . . . . . . . 60 6.13.2 clock doubling option . . . . . . . . . . . . . . . . . . . 60 7 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 62 8 static characteristics . . . . . . . . . . . . . . . . . . . 62 9 dynamic characteristics . . . . . . . . . . . . . . . . . 65 9.1 explanation of symbols . . . . . . . . . . . . . . . . . 66 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . 74 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 77 12 revision history . . . . . . . . . . . . . . . . . . . . . . . 78 13 legal information . . . . . . . . . . . . . . . . . . . . . . 79 13.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 79 13.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14 contact information . . . . . . . . . . . . . . . . . . . . 79 15 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 |
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